IDT82V2108PX IDT, Integrated Device Technology Inc, IDT82V2108PX Datasheet - Page 34

• Manufacturer Part Number: IDT82V2108PX
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX

IDT82V2108
3.6
T1/J1 ONLY
format in T1/J1 mode. The standard of BOM is defined in ANSI T1.403
and in TR-TSY-000194. This block of each framer operates indepen-
dently.
the F-bit in the ESF format (refer to Table 4). The six ‘X’s represent the
message. The BOM is declared only when the pattern is matched and
the received message is identical 4 out of 5 times or 8 out of 10 times.
The identification time is determined by the AVC (b1, T1/J1-02AH). After
the BOM is declared, the BOM is loaded into the BOC[5:0] (b5~0, T1/J1-
02BH). However, the BOM does not include all ones code in both T1 and
J1 mode.
be idle code. The pattern of the idle code is ‘FFFF’ in T1 mode and
‘FF7E’ in J1 mode. When the received data is 4 out of 5 times or 8 out of
10 times identical with the pattern, the idle code is declared. The identifi-
cation time is determined by the AVC (b1, T1/J1-02AH).
declared, the BOCI (b6, T1/J1-02BH) will be set. When the idle code is
declared, the IDLEI (b7, T1/J1-02BH) will be set. If the BOCE (b0, T1/
J1-02AH) and IDLE (b2, T1/J1-02AH) are set to ‘1’ respectively, the cor-
responding condition will cause an interrupt on the INT pin.
Functional Description
The Bit Oriented Message (BOM) can only be received in the ESF
The BOM pattern is ‘111111110XXXXXX0’ which occupies the DL of
When the BOM is converted into non-BOM, the received data will
There are two interrupt sources in this block. When the BOM is
BIT-ORIENTED MESSAGE RECEIVER (RBOM) -
24
3.7
T1/J1 ONLY
deactivate codes only in framed or unframed T1/J1 data stream. The
Inband Loopback Code Detector of each framer operates independently.
deactivate code whose length and the content are programmed in the
ASEL[1:0] (b1~0, T1/J1-03CH) / DSEL[1:0] (b3~2, T1/J1-03CH) and the
ACT[7:0] (b7~0, T1/J1-03EH) / DACT[7:0] (b7~0, T1/J1-03FH) respec-
tively. In framed mode, the F-bit can be chosen by the IBCD_IDLE (b5,
T1/J1-000H) to compare with the target activate/deactivate code or not.
In unframed mode, all 193 bits are compared with the target activate/
deactivate code. If the received data stream matches the target activate
or deactivate code and repeats for a 39.8 ms period, the LBACP (b7, T1/
J1-03DH) or LBDCP (b6, T1/J1-03DH) will indicate the appearance of
the corresponding code. 2, 20 or 200 bit-error tolerance within each 39.8
ms period is permitted by setting the IBCD_ERR[1:0] (b5~4, T1/J1-
03CH). However, even if the F-bit is compared, whether it is matched or
not, the result will not cause bit errors, that is, the comparison result of
the F-bit is passed over.
vate code and repeats for 5.1 sec, the LBA (b1, T1/J1-03DH) / LBD (b0,
T1/J1-03DH) will indicate the detection of the inband loopback code.
The code sequences detection and timing is compatible with the specifi-
cations in T1.403, TA-TSY-000312 and TR-TSY-000303.
rupt sources in the IBCD block. That is, when the value in the Status
Register (LBA [b1, T1/J1-03DH] or LBD [b0, T1/J1-03DH]) changes, its
corresponding Interrupt Indication Register (LBAI [b3, T1/J1-03DH] or
LBDI [b2, T1/J1-03DH]) will be logic 1. A logic 1 on the Interrupt Indica-
tion Register will cause an interrupt on the INT pin if the corresponding
Interrupt Enable Register (LBAE [b5, T1/J1-03DH] or LBDE [b4, T1/J1-
03DH]) is logic 1.
The Inband Loopback Code Detector can track loopback activate/
The received data stream is compared with the target activate/
When the received data stream matches the target activate/deacti-
The status changes of the activate or deactivate code are the inter-
INBAND LOOPBACK CODE DETECTOR (IBCD) -
T1 / E1 / J1 OCTAL FRAMER
March 5, 2009