PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 106

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Figure 60
Data Sheet
EXMD.RFBS=11
so after the first 4
bytes of a new frame
have been stored in the
fifo an receive pool full
interrupt ISTAD.RPF
is set.
The HDLC
receiver has
written further
data into the FIFO.
When a frame
is complete, a
status byte (RSTAD)
is appended.
Meanwhile two
more short frames
have been
received.
HDLC
Receiver
HDLC
Receiver
When the RFACC detects 16 valid bytes,
it sets an RPF interrupt. The µP reads the 16 bytes
and acknowledges the transfer by setting CMDRD.RMC.
This causes the space occupied by the 16 bytes being
released.
RFIFO Operation
RAM
RAM
RSTA
RSTA
RSTA
µP
µP
32
16
32
16
8
4
8
RFIFO ACCESS
RFIFO ACCESS
CONTROLLER
CONTROLLER
RFBS=01
RFBS=11
RFACC
RFACC
106
The µP has read
the 4 bytes, sets
RFBS=01 (16 bytes)
and completes the
block transfer by
an CMDRx.RMC command.
Following CMDRx.RMC
the 4 bytes of the
last block are
deleted.
RMC
EXMD.RFBS=01
RMC
Description of Functional Blocks
Receiver
HDLC
Receiver
HDLC
After the RMC acknowledgement the
RFACC detects an RSTA byte, i.e. end of
the frame, therefore it asserts
an RME interupt and increments the
RBC counter by 2.
RAM
RAM
RSTA
RSTA
RSTA
µP
32
16
32
16
8
4
8
RFIFO ACCESS
RFIFO ACCESS
CONTROLLER
CONTROLLER
ISAC-SX TE
RFBS=01
RFBS=01
RFACC
RFACC
PSB 3186
2003-01-30