PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 169

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MODE2
ID
• If RSS = ’10’ is selected the following two reset sources generate a reset pulse of
After a reset pulse generated by the ISAC-SX TE and the corresponding interrupt (WOV
or CIC) the actual reset source can be read from the ISTA.
4.4.6
Value after reset: 00
INT_POL ... Interrupt Polarity
Selects the polarity of the interrupt pin INT.
0: low active with open drain characteristic (default)
1: high active with push pull characteristic
PPSDX ... Push/Pull Output for SDX (SCI Interface)
0: The SDX pin has open drain characteristic
1: The SDX pin has push/pull characteristic
4.4.7
Value after reset: 01
Data Sheet
125 µs £ t £ 250µs at the RSTO pin:
- External (Subscriber) Awake (EAW)
The EAW input pin serves as a request signal from the subscriber to initiate the awake
function in a terminal and generates a reset pulse (in TE mode only).
- Exchange Awake (C/I Code)
A C/I Code change generates a reset pulse.
7
7
MODE2 - Mode2 Register
ID - Identification Register
0
0
H
H
0
0
0
0
169
INT_
POL
DESIGN
0
Detailed Register Description
0
0
PPSDX RD/WR (63)
0
ISAC-SX TE
PSB 3186
2003-01-30
RD (64)