PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 108

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Figure 61
Figure 62
that a long frame (68 byte) followed by two short frames (12 byte each) are received. The
FIFO threshold (block size) is set to 32 byte in this example:
• After 32 byte of frame 1 have been received an RPF interrupt is generated to indicate
Data Sheet
that a data block can be read from the RFIFOD.
gives an example of an interrupt controlled reception sequence, supposed
Data Reception Procedures
*
1)
In case of RME the last byte in RFIFO contains
the receive status information RSTA
N
Read Counter
RD_Count := RFBS
or
RD_Count := RBC
Read RD_Count
bytes from RFIFO
Change Block Size
Write EXMR.RFBS
(optional)
Receive Message
Complete
Write RMC
Message End
Pool Full
Receive
Receive
START
RME
RPF
?
?
N
Y
108
Y
*
1)
RBC = RBCH + RBCL register
RFBS: Refer to EXMR register
Read RBC
RD_Count := RBC
Description of Functional Blocks
x
HDLC_Rflow.vsd
x
ISAC-SX TE
PSB 3186
2003-01-30