PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 137

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

RBCHD
TEI1
4.1.13
Value after reset: 00
OV ... Overflow
A ’1’ in this bit position indicates a message longer than (2
RBC8-11 ... Receive Byte Count
Four most significant bits of the total number of bytes in a received message (see
RBCLD register).
Note: Normally RBCHD and RBCLD should be read by the microcontroller after an
4.1.14
Value after reset: FF
TEI1 ... Terminal Endpoint Identifier
In all message transfer modes except in transparent modes 0, 1 and extended
transparent mode, TEI1 is used by the ISAC-SX TE for address recognition. In the case
of a two-byte address field, it contains the value of the first programmable Terminal
Endpoint Identifier according to the ISDN LAPD-protocol.
In non-automodes with one-byte address field, TEI1 is a command address, according
to X.25 LAPB.
EA1 ... Address field Extension bit
This bit is set to ’1’ according to HDLC/LAPD.
Data Sheet
RME-interrupt in order to determine the number of bytes to be read from the
RFIFOD, and the total message length. The contents of the registers are valid only
after an RME or RPF interrupt, and remain so until the frame is acknowledged via
the RMC bit or RRES.
7
7
RBCHD - Receive Frame Byte Count High D-Channel
TEI1 - TEI1 Register 1
0
H
H
0
.
0
TEI1
OV
137
RBC11
Detailed Register Description
12
- 1) = 4095 bytes .
0
0
RBC8
EA1
ISAC-SX TE
PSB 3186
2003-01-30
WR (27)
RD (27)