PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 99

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Figure 57
S-Bus D-channel Access Control in the ISAC-SX TE
The above described priority mechanism is fully implemented in the ISAC-SX TE. For
this purpose the D-channel collission detection according to ITU I.430 must be enabled
by setting MODED.DIM2-0 to ’0x1’. In this case the transceiver continuously compares
the received E-echo bits with its own transmitted D data bits.
Depending on the priority class selected, 8 or 10 consecutive ONEs (high priority level,
priority 8) need to be detected before the transceiver sends valid D-channel data on the
upstream D-bits on S. In low priority level (priority 10) 10 or 11 consecutive ONEs are
required.
The priority class (priority 8 or priority 10) is selected by transferring the appropriate
activation command via the Command/Indication (C/I) channel of the IOM-2 interface to
the transceiver. If the activation is initiated by a TE, the priority class is selected implicitly
by the choice of the activation command. If the S-interface is activated from the NT, an
activation command selecting the desired priority class should be programmed at the TE
on reception of the activation indication (AI8 or AI10). In the activated state the priority
class may be changed whenever required by simply programming the desired activation
request command (AR8 or AR10).
Data Sheet
D-channel
D-channel
D-channel
control
control
control
D-Channel Access Control on the S-Interface
TE 1
TE 2
.
.
.
TE 8
transceiver
transceiver
transceiver
S-
S-
S-
99
S-Interface
Description of Functional Blocks
D-Bits
E-Bits
NT
3086_10
U-Interface
ISAC-SX TE
PSB 3186
2003-01-30