PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 54

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.4
Figure 28
a 7.68 MHz clock signal (f
DCL (1536 kHz) and BCL (768 kHz) synchronous to the received S/T frames.
The FSC signal is used to generate the pulse lengths of the different reset sources C/I
Code, EAW pin and Watchdog (see
in
Figure 28
Table 9
Signal
FSC
DCL
BCL
DU
DD
Data Sheet
Table
XTAL
7.68 MHz
9.
shows the clock system of the ISAC-SX TE. The oscillator is used to generate
Clock Generation
Clock System of the ISAC-SX TE
IOM-2 Clocks
OSC
Function
o:8 kHz (DIS_TR=0), normal mode
i:8 kHz (DIS_TR=1), S transceiver disabled
o:1536 kHz (DIS_TR=0), normal mode
i:1536/768 kHz (DIS_TR=1), S transceiver disabled
o:768 kHz
i
o
*2)
*2)
f
XTAL
XTAL
DPLL
). The DPLL generates the IOM-2 clocks FSC (8 kHz),
Chapter
Reset
Generation
SW Reset
C/I
EAW
Watchdog
54
3.2.4). The IOM-2 clocks are summarized
Description of Functional Blocks
*1)
FSC
DCL
BCL
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
125 µs £ t £ 250 µs
*1)
ISAC-SX TE
3186_06
PSB 3186
2003-01-30