PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 170

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

SRES
TIMR2
DESIGN ... Design Number
The design number allows to identify different hardware designs of the ISAC-SX TE by
software.
01
(all other codes reserved)
4.4.8
Value after reset: 00
RES_xx ... Reset Functional Block xx
A reset can be activated on the functional block C/I-handler, Monitor channel, D-channel,
IOM handler, S-transceiver and to pin RSTO.
Setting one of these bits to “1” causes the corresponding block to be reset for a duration
of 4 BCL clock cycles, except RES_RSTO which is activated for a duration of
125 ... 250µs. The bits are automatically reset to “0” again.
4.4.9
Value after reset: 00
TMD ... Timer Mode
Timer 2 can be used in two different modes of operation.
0: Count Down Timer. An interrupt is generated only once after a time period of
1: Periodic Timer. An interrupt is periodically generated every 1 ... 63 ms (see CNT).
CNT ... Timer Counter
0: Timer off.
1 ... 63:Timer period = 1 ... 63 ms
Data Sheet
H
1...63 ms.
: V 1.4
7
7
SRES - Software Reset Register
RES_
TIMR2 - Timer 2 Register
TMD
CI
H
H
0
0
0
RES_
MON
170
RES_
DCH
CNT
RES_
IOM
Detailed Register Description
RES_
TR
0
0
RSTO
RES_
ISAC-SX TE
RD/WR (65)
PSB 3186
2003-01-30
WR (64)