PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 46

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Figure 20
3.3.5
The receiver consists of a differential input stage, a peak detector and a set of
comparators. Additional noise immunity is achieved by digital oversampling after the
comparators. A simplified equivalent circuit of the receiver is shown in
Figure 21
The input stage works together with external 10 k W resistors to match the input voltage
to the internal thresholds. The data detection threshold Vref is continuously adapted
between a maximal (Vrefmax) and a minimal (Vrefmin) reference level related to the line
level. The peak detector requires maximum 2 m s to reach the peak value while storing
the peak level for at least 250 m s (RC > 1 ms).
The additional level detector for power up/down control works with a fixed thresholds
VrefLD. The level detector monitors the line input signals to detect whether an INFO is
present. When closing an analog loop it is therefore possible to indicate an incoming
signal during activated loop.
Data Sheet
10 kW
10 kW
VCM+0.525V
VCM
VCM-0.525V
VCM-0.525V
VCM
VCM+0.525V
SR2
SR1
Receiver Characteristics
Equivalent Internal Circuit of the Transmitter Stage
Equivalent Internal Circuit of the Receiver Stage
40 kW
40 kW
'+0'
'+0'
'-0'
'-0'
'1'
'1'
Level
100 kW
+
+
-
-
VCM
V=1
V=1
VCM
46
TR_CONF2.DIS_TX
Vrefmin
Description of Functional Blocks
Peak
Detector
Vref+
Vref-
VrefLD
Figure
ISAC-SX TE
Negative detected
Positive detected
Level detected
'+0' '1' '-0'
PSB 3186
SX1
SX2
2003-01-30
21.
21150_28
reccirc