PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 63

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.5.1.3
Command
Activation Request with
priority class 8
Activation Request with
priority class 10
Activation Request Loop ARL
Deactivation Indication
Reset
Timing
Test mode SSP
Test mode SCP
Note: In the activated states (AI8, AI10 or AIL indication) the 2B+D channels are only
Data Sheet
transferred transparently to the S/T interface if one of the three “Activation
Request” commands is permanently issued.
C/I Codes (TE)
Abbr. Code Remark
AR8
AR10 1001 Activation requested by the ISAC-SX,
DI
RES
TIM
SSP
SCP
1000 Activation requested by the ISAC-SX,
1010 Activation requested for the internal or
1111 Deactivation Indication
0001 Reset of the layer-1 statemachine
0000 Layer-2 device requires clocks to be activated
0010 One AMI-coded pulse transmitted in each
0011 AMI-coded pulses transmitted continuously,
D-channel priority set to 8 (see note)
D-channel priority set to 10 (see note)
external Loop A (see note).
For a non transparent internal loop bit DIS_TX
of register TR_CONF2 has to be set to ’1’
additionally.
frame, resulting in a frequency of the
fundamental mode of 2 kHz
resulting in a frequency of the fundamental
mode of 96 kHz
63
Description of Functional Blocks
ISAC-SX TE
PSB 3186
2003-01-30