PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 93

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.7.3.6
Figure 52
Data Receive interrupt status MDR has two enable bits, MONITOR Receive interrupt
Enable (MRE) and MR bit Control (MRC). The MONITOR channel End of Reception
MER, MONITOR channel Data Acknowledged MDA and MONITOR channel Data Abort
MAB interrupt status bits have a common enable bit MONITOR Interrupt Enable MIE.
MRE prevents the occurrence of MDR status, including when the first byte of a packet is
received. When MRE is active (1) but MRC is inactive, the MDR interrupt status is
generated only for the first byte of a receive packet. When both MRE and MRC are
active, MDR is always generated and all received MONITOR bytes - marked by a 1-to-0
transition in MX bit - are stored. (Additionally, an active MRC enables the control of the
MR handshake bit according to the MONITOR channel protocol.)
Figure 52
3.7.4
The Command/Indication channel carries real-time status information between the
ISAC-SX TE and another device connected to the IOM-2 interface.
1) One C/I channel (called C/I0) conveys the commands and indications between the
layer-1 and the layer-2 parts of the ISAC-SX TE. It can be accessed by an external
layer-2 device e.g. to control the layer-1 activation/deactivation procedures. C/I0 channel
access may be arbitrated via the TIC bus access protocol. In this case the arbitration is
done in IOM-2 channel 2 (see
The C/I0 channel is accessed via register CIR0 (in receive direction, layer-1 to layer-2)
and register CIX0 (in transmit direction, layer-2 to layer-1). The C/I0 code is four bits
long. A listing and explanation of the layer-1 C/I codes can be found in
In the receive direction, the code from layer-1 is continuously monitored, with an interrupt
Data Sheet
shows the MONITOR interrupt structure of the ISAC-SX TE. The MONITOR
MONITOR Interrupt Logic
C/I Channel Handling
TRAN
MASK
WOV
MOS
ICD
ST
CIC
Interrupt
MONITOR Interrupt Structure
TRAN
ISTA
WOV
MOS
ICD
ST
CIC
Figure
36).
93
Description of Functional Blocks
MOCR
MRE
MIE
MOSR
MER
MAB
MDR
MDA
Chapter
ISAC-SX TE
PSB 3186
2003-01-30
3.5.2.