PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 40

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Figure 15
3.3.1
Transmission over the S/T-interface is performed at a rate of 192 kbit/s. 144 kbit/s are
used for user data (B1+B2+D), 48 kbit/s are used for framing and maintenance
information.
Line Coding
The following figure illustrates the line code. A binary ONE is represented by no line
signal. Binary ZEROs are coded with alternating positive and negative pulses with two
exceptions:
For the required frame structure a code violation is indicated by two consecutive pulses
of the same polarity. These two pulses can be adjacent or separated by binary ONEs.
In bus configurations a binary ZERO always overwrites a binary ONE.
Data Sheet
1) The maximum line attenuation tolerated by the ISAC-SX TE is 7 dB at 96 kHz.
TE
ISAC-SX TE
TR
TE1
ISAC-SX TE
S/T-Interface Coding
Wiring Configurations in User Premises
£ 25 m
TR
TE1
TR
ISAC-SX TE
....
£ 10 m
£ 500 m
TE8
ISAC-SX TE
£ 1000 m
£ 100 m
....
£ 10 m
TE8
1)
ISAC-SX TE
40
TR
TR
TR
Description of Functional Blocks
TR: Terminating Resistor
NT / LT-S
NT / LT-S
ISAC-SX
ISAC-SX
ISAC-SX
LT-S
Point-to-Point
Configuration
Short
Passive Bus
Extended
Passive Bus
ISAC-SX TE
PSB 3186
3186_20
2003-01-30