PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 148

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PSB3186FV14XT

Manufacturer Part Number
PSB3186FV14XT
Description
Manufacturer
Lantiq
Datasheet

Specifications of PSB3186FV14XT

Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
SQRR2
SQRR3
ISTATR
4.2.7
Value after reset: 00
SQR21-24, SQR31-34... Received S Bits
Received S bits in frames 2, 7, 12 and 17 (SQR21-24, subchannel 2),
and in frames 3, 8, 13 and 18 (SQR31-34, subchannel 3).
4.2.8
Value after reset: 00
SQR41-44, SQR51-54... Received S Bits
Received S bits in frames 4, 9, 14 and 19 (SQR41-44, subchannel 4),
and in frames 5, 10, 15 and 20 (SQR51-54, subchannel 5).
4.2.9
Value after reset: 00
For all interrupts in the ISTATR register the following logical states are defined:
0: Interrupt is not acitvated
1: Interrupt is acitvated
x ... Reserved
Bits set to “1” in this bit position must be ignored.
Data Sheet
7
7
7
SQR21 SQR22 SQR23 SQR24 SQR31 SQR32 SQR33 SQR34
SQR41 SQR42 SQR43 SQR44 SQR51 SQR52 SQR53 SQR54
SQRR2 - S/Q-Channel Receive Register 2
SQRR3 - S/Q-Channel Receive Register 3
ISTATR - Interrupt Status Register Transceiver
x
H
H
H
x
x
x
148
LD
RIC
Detailed Register Description
SQC
0
0
0
SQW
ISAC-SX TE
PSB 3186
2003-01-30
RD (36)
RD (37)
RD (38)

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