PSB3186FV14XT Lantiq, PSB3186FV14XT Datasheet - Page 155

• Manufacturer Part Number: PSB3186FV14XT
• Manufacturer: Lantiq

Specifications of PSB3186FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Note: The timeslot for the C/I1 handler cannot be programmed but is fixed to IOM
D_EN_D ... Enable D-timeslot for D-channel controller
D_EN_B2 ... Enable B2-timeslot for D-channel controller
D_EN_B1 ... Enable B1-timeslot for D-channel controller
These bits are used to select the timeslot length for the D-channel HDLC controller
access as it is capable to access not only the D-channel timeslot. The host can
individually enable two 8-bit timeslots B1- and B2-channel (D_EN_B1, D_EN_B2) and
one 2-bit timeslot D-channel (D_EN_D) on IOM-2. The position is selected via CS2-0.
0: D-channel controller does not access timeslot data B1, B2 or D, respectively
1: D-channel controller does access timeslot data B1, B2 or D, respectively
CS2-0 ... Channel Select for D-channel controller
This register is used to select one of eight IOM channels. If enabled, the D-channel data
is connected to the corresponding timeslots of that IOM channel.
Note: It should be noted that writing DCI_CR.CS2-0 will also write to DCIC_CR.CS2-0
4.3.5.1
Value after reset: 00
DCIC_CR
Write access to this register is possible if IOM_CR.CI_CS = 0 or IOM_CR.CI_CS = 1.
Read access to this register is possible only if IOM_CR.CI_CS = 1.
CS2-0 ... Channel Select for C/I0 Handler
This register is used to select one of eight IOM channels. If enabled, the data of the
C/I0-handler is connected to the corresponding C/I0 timeslots of that IOM channel.
Data Sheet
channel 1.
and therefore modify the channel selection for the data of the
C/I0 handler.
DCIC_CR - Control Register for CI0 Handler (IOM_CR.CI_CS=1)
7
0
H
0
0
0
155
0
Detailed Register Description
CS2-0
0
ISAC-SX TE
RD/WR (13)
PSB 3186
2003-01-30