PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet
PI7C7300ANAE
Specifications of PI7C7300ANAE
Available stocks
Related parts for PI7C7300ANAE
PI7C7300ANAE Summary of contents
Page 1
PI7C7300A PCI-to-PCI BRIDGE 2380 BERING DRIVE, SAN JOSE, CA 95131 TELEPHONE: 1-877-PERICOM (1-877-737-4266) EMAIL: INTERNET: 3-PORT REVISION 1.09 FAX: 408-435-1100 SOLUTIONS@PERICOM.COM HTTP://WWW.PERICOM.COM ...
Page 2
... Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use ...
Page 3
REVISION HISTORY Revision Date 1.01 9/25/01 1.02 10/25/01 1.03 10/29/01 1.04 11/12/01 1.05 12/19/01 1.06 06/04/02 1.07 08/22/02 1.08 09/09/03 1.09 09/25/03 Description Corrected the description for bits 4:2 in both Configuration register 1 and configuration register 2 at offset ...
Page 4
This page intentionally left blank. Page 4 OF 109 PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 09/25/03 Revision 1.09 ...
Page 5
TABLE OF CONTENTS 1 INTRODUCTION .............................................................................................................................. 11 2 BLOCK DIAGRAM........................................................................................................................... 12 3 SIGNAL DEFINITIONS ................................................................................................................... 13 3.1 SIGNAL TYPES .......................................................................................................................... 13 3.2 PRIMARY BUS INTERFACE SIGNALS ................................................................................... 13 3.3 SECONDARY BUS INTERFACE SIGNALS............................................................................. 15 3.4 CLOCK SIGNALS....................................................................................................................... 17 3.5 MISCELLANEOUS ...
Page 6
CONCURRENT MODE OPERATION ....................................................................................... 40 5 ADDRESS DECODING .................................................................................................................... 40 5.1 ADDRESS RANGES ................................................................................................................... 40 5.2 I/O ADDRESS DECODING ........................................................................................................ 41 5.2.1 I/O BASE AND LIMIT ADDRESS REGISTER..................................................................... 42 5.2.2 ISA MODE............................................................................................................................ 42 5.3 MEMORY ADDRESS DECODING............................................................................................ 43 5.3.1 ...
Page 7
SUPPORTED COMMANDS ........................................................................................................ 69 13.1 PRIMARY INTERFACE ............................................................................................................. 69 13.2 SECONDARY INTERFACE ....................................................................................................... 70 14 CONFIGURATION REGISTERS ............................................................................................... 70 14.1 CONFIGURATION REGISTER 1 AND 2 .................................................................................. 72 14.1.1 VENDOR ID REGISTER – OFFSET 00h............................................................................. 72 14.1.2 DEVICE ID REGISTER ...
Page 8
SECONDARY SUCCESSFUL MEMORY WRITE COUNTER REGISTER – OFFSET 8Ch .......................................................................................................................................... 89 14.1.45 PRIMARY SUCCESSFUL I/O READ COUNTER REGISTER – OFFSET 90h ............... 89 14.1.46 PRIMARY SUCCESSFUL I/O WRITE COUNTER REGISTER – OFFSET 94h.............. 89 14.1.47 PRIMARY SUCCESSFUL MEMORY READ ...
Page 9
T 4-5 READ TRANSACTION PREFETCHING ................................................................................ 28 ABLE T 4-6 DEVICE NUMBER TO IDSEL S1_AD OR S2_AD PIN MAPPING ....................................... 32 ABLE T 4-7 DELAYED WRITE TARGET TERMINATION RESPONSE.................................................. 37 ABLE T 4-8 RESPONSE TO POSTED WRITE TARGET TERMINATION ............................................... ...
Page 10
This page intentionally left blank. Page 10 OF 109 PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 09/25/03 Revision 1.09 ...
Page 11
... INTRODUCTION PRODUCT DESCRIPTION The PI7C7300A is Pericom Semiconductor’s second-generation PCI-PCI Bridge designed to be fully compliant with the 32-bit, 66MHz implementation of the PCI Local Bus Specification, Revision 2.2. The PI7C7300A supports only synchronous bus transactions between devices on the Primary Bus running at 33MHz to 66MHz and the Secondary Buses operating at either 33MHz or 66MHz ...
Page 12
BLOCK DIAGRAM 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page 12 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...
Page 13
SIGNAL DEFINITIONS 3.1 SIGNAL TYPES Signal Type PI PIU PID PO PB PSTS PTS POD 3.2 PRIMARY BUS INTERFACE SIGNALS Name P_AD[31:0] P_CBE[3:0] P_PAR P_FRAME# Description PCI input (3.3V, 5V tolerant) PCI input (3.3V, 5V tolerant) with weak pull-up ...
Page 14
Name Pin # Type P_IRDY# V13 PSTS P_TRDY# U13 PSTS P_DEVSEL# Y14 PSTS P_STOP# W14 PSTS P_LOCK# V14 PSTS P_IDSEL Y10 PI P_PERR# Y15 PSTS P_SERR# W15 POD P_REQ# W6 PTS P_GNT P_RESET Page 14 OF ...
Page 15
Name P_M66EN 3.3 SECONDARY BUS INTERFACE SIGNALS Name S1_AD[31:0], S2_AD[31:0] S1_CBE[3:0], S2_CBE[3:0] S1_PAR, S2_PAR S1_FRAME#, S2_FRAME# Pin # Type Description V18 PI Primary Interface 66MHz Operation. This input is used to specify if PI7C7300A is capable of running at 66MHz. ...
Page 16
Name Pin # Type S1_IRDY#, H19, PSTS S2_IRDY# B2 S1_TRDY#, H18, PSTS S2_TRDY# A2 S1_DEVSEL#, J20, PSTS S2_DEVSEL# D3 S1_STOP#, J19, PSTS S2_STOP# C3 S1_LOCK#, J18, PSTS S2_LOCK# B3 S1_PERR#, J17, PSTS S2_PERR# D4 S1_SERR#, K20, PI S2_SERR# C4 S1_REQ#[7:0], ...
Page 17
Name S_CFN# 3.4 CLOCK SIGNALS Name P_CLK S1_CLKOUT [7:0] S2_CLKOUT [7:0] 3.5 MISCELLANEOUS SIGNALS Name BYPASS PLL_TM S_CLKIN SCAN_TM# SCAN_EN 3.6 COMPACT PCI HOT-SWAP SIGNALS Name LOO HS_SW# HS_EN Pin # Type Description Y2 PIU Secondary Bus Central Function Control ...
Page 18
Name ENUM# 3.7 JTAG BOUNDARY SCAN SIGNALS Name TCK TMS TDO TDI TRST# 3.8 POWER AND GROUND Name VDD VSS AVCC AGND 3.9 PI7C7300A PBGA PIN LIST Pin # Name A1 S2_CBE[2] A3 VSS A5 VSS A7 S2_CBE[0] A9 S2_AD[2] ...
Page 19
Pin # Name Type A17 VSS - A19 S1_CLKOUT[0] PTS B1 S2_AD[16 S2_LOCK# PSTS B5 S2_AD[14 S2_AD[ S2_AD[3] PB B11 S1_REQ#[7] PIU B13 S1_GNT#[5] PO B15 S1_CLKOUT[3] PTS B17 S1_REQ#[0] PIU B19 S1_AD[30] PB ...
Page 20
Pin # Name Type L11 VSS - L17 VDD - L19 S1_AD[14 S2_REQ#[2] PIU M3 S2_GNT#[ VSS - M11 VSS - M17 S1_AD[10] PB M19 S1_AD[11 VSS - N3 S2_CLKOUT[4] PTS N17 S1_AD[6] PB ...
Page 21
Pin # Name Y17 P_AD[11] Y19 P_AD[5] 4 PCI BUS OPERATION This Chapter offers information about PCI transactions, transaction forwarding across PI7C7300A, and transaction termination. The PI7C7300A has three 128-byte buffers for buffering of upstream and downstream transactions. commands, and ...
Page 22
To generate special cycle transactions on other PCI buses, either upstream or downstream, Type 1 configuration write must be used. ! PI7C7300A neither ...
Page 23
A transfer of data occurs only when both IRDY# and TRDY# are asserted during the same PCI clock cycle. The last data phase of a transaction is indicated when FRAME# is de-asserted and both TRDY# and IRDY# are asserted, or ...
Page 24
On the following cycle, PI7C7300A drives the first DWORD of write data and continues to transfer write data until all write data corresponding to that transaction is delivered, or until a target termination is ...
Page 25
When a write transaction is first detected on the initiator bus, and PI7C7300A forwards delayed transaction, PI7C7300A claims the access by asserting DEVSEL# and returns a target retry to the initiator. During the address phase, PI7C7300A samples ...
Page 26
Table 4-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES Type of Transaction Delayed Write Posted Memory Write Posted Memory Write Posted Memory Write and Invalidate Posted Memory Write and Invalidate Note 1. Memory write disconnect control bit is bit 1 of the ...
Page 27
Prefetchable behavior is used for memory read line and memory read multiple transactions, as well as for memory read transactions that fall into prefetchable memory space. The amount of data that is pre-fetched depends on the type of transaction. The ...
Page 28
Memory Read Memory Read Memory Read Line Memory Read Line Memory Read Multiple Memory Read Multiple - does not matter prefetchable or non-prefetchable * don’t care Table 4-5 READ TRANSACTION PREFETCHING Type of Transaction I/O Read Configuration ...
Page 29
If PI7C7300A is unable to obtain read data from the target after 2 (maximum) attempts, PI7C7300A will report a system error. The number of attempts is programmable. PI7C7300A also asserts P_SERR# if the primary SERR# enable bit is set in ...
Page 30
PI7C7300A has the capability to post multiple delayed read requests maximum of four in each direction initiator starts a read transaction that matches the address and read command of a read transaction that is already ...
Page 31
The bus command is a configuration read or configuration write transaction. ! Lowest two address bits P_AD[1:0] must be 00b. ! Signal P_IDSEL must be asserted. Function code is either 0 for configuration space of S1 for ...
Page 32
Decodes the device number and drives the bit pattern specified in Table 4-6 on S1_AD[31:16] or S2_AD[31:16] for the purpose of asserting the device’s IDSEL signal. ! Sets S1_AD[15:11] or S2_AD[15:11 Leaves unchanged the function number ...
Page 33
When PI7C7300A detects a Type 1 configuration transaction intended for a PCI bus downstream from the secondary bus, PI7C7300A forwards the transaction unchanged to the secondary bus. Ultimately, this transaction is translated to a Type 0 configuration command or to ...
Page 34
The register number in address bits AD[7:2] is equal to 000000b. ! The bus number is equal to the value in the secondary bus number register in configuration space for downstream forwarding or equal to the value in the ...
Page 35
STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of the transaction. ! Target disconnect without data transfer STOP# and DEVSEL# asserted with TRDY# de-asserted after previous data transfers have been made. Indicates that no ...
Page 36
For delayed read and write transactions, PI7C7300A is able to reflect the master abort condition back to the initiator. When PI7C7300A detects a master abort in response to a delayed transaction, and when the initiator repeats the transaction, PI7C7300A does ...
Page 37
PI7C7300A makes 2 of target retry. Table 4-7 DELAYED WRITE TARGET TERMINATION RESPONSE Target Termination Normal Target Retry Target Disconnect Target Abort After the PI7C7300A makes 2 on the target bus, PI7C7300A asserts P_SERR# if the SERR# enable bit (bit ...
Page 38
DELAYED READ TARGET TERMINATION RESPONSE When PI7C7300A initiates a delayed read transaction, the abnormal target responses can be passed back to the initiator. Other target responses depend on how much data the initiator requests. Table 4-9 shows the response ...
Page 39
Target response has been received but has not progressed to the head of the return queue. ! The delayed transaction queue is full, and the transaction cannot be queued transaction with the same address and command has ...
Page 40
PI7C7300A returns a target disconnect to an initiator when one of the following conditions is met: ! PI7C7300A hits an internal address boundary. ! PI7C7300A cannot accept any more write data. ! PI7C7300A has no more read data to deliver. ...
Page 41
Two 32-bit I/O address ranges ! Two 32-bit memory-mapped I/O (non-prefetchable memory) ranges ! Two 32-bit prefetchable memory address ranges Transactions falling within these ranges are forwarded downstream from the primary PCI bus to the two secondary PCI buses. ...
Page 42
PCI buses are idle. 5.2.1 I/O BASE AND LIMIT ADDRESS REGISTER PI7C7300A implements one set of I/O base and limit address registers in configuration space that ...
Page 43
I/O space (address bits [31:16] are 0000h). When the ISA enable bit is set, PI7C7300A does not forward downstream any I/O transactions addressing the top 768 bytes of each aligned ...
Page 44
The memory-mapped I/O base address and memory-mapped I/O limit address registers define an address range that PI7C7300A uses to determine when to ...
Page 45
PI7C7300A does not respond to any transactions that fall outside this address range on the primary interface and forwards those transactions upstream from the secondary interface (provided that they do not fall into ...
Page 46
When a VGA-compatible device exists downstream from PI7C7300A, set the VGA mode bit in the bridge control register in configuration space to enable VGA mode. When PI7C7300A is operating in VGA mode, it forwards downstream those transactions addressing the VGA ...
Page 47
Posted write transactions, comprised of memory write and memory write and invalidate transactions. Posted write transactions complete at the source before they complete at the destination; that is, data is written into intermediate data buffers before it reaches the target. ...
Page 48
The ordering relationship of a transaction with respect to other transactions is determined when the transaction completes, that is, when a transaction ends with a termination other than target retry. ! Requests terminated with target retry can be accepted ...
Page 49
Note that delayed completion transactions cross PI7C7300A in the direction opposite that of the corresponding delayed requests. 1. Posted write transactions must complete on the target bus in the order in which they were received on the initiator ...
Page 50
System hardware guarantees that write buffers are flushed before interrupts are forwarded. PI7C7300A does not have a hardware mechanism to guarantee data synchronization for posted write transactions. Therefore, all posted write transactions must be followed by a read operation, ...
Page 51
If the parity error response bit is set in the bridge control register, PI7C7300A does not claim the transaction with S1_DEVSEL# or S2_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error response bit ...
Page 52
PI7C7300A sets the data parity detected bit in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register. ! PI7C7300A forwards the bad parity with the data back to the ...
Page 53
When PI7C7300A detects a parity error on the write data for the initial delayed write request transaction, the following events occur the parity-error-response bit corresponding to the initiator bus is set, PI7C7300A asserts TRDY# to ...
Page 54
For downstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C7300A has write status to return, the following events occur: ! PI7C7300A first asserts P_TRDY# and then asserts P_PERR# two cycles later, if the ...
Page 55
POSTED WRITE TRANSACTIONS During downstream posted write transactions, when PI7C7300A responds as a target, it detects a data parity error on the initiator (primary) bus and the following events occur: ! PI7C7300A asserts P_PERR# two cycles after the data ...
Page 56
During upstream write transactions, when a data parity error is reported on the target (primary) bus by the target’s assertion of P_PERR#, the following events occur: ! PI7C7300A sets the data parity detected bit in the status register, if the ...
Page 57
Primary Detected Transaction Type Parity Error Bit 0 Delayed Write X = don’t care Table 7-2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when PI7C7300A detects ...
Page 58
Table 7-4 shows setting the data parity detected bit in the status register of secondary interface. This bit is set under the following conditions: ! The PI7C7300A must be a master on the secondary bus. ! The parity error response ...
Page 59
Delayed Write 1 Delayed Write 1 Delayed Write X = don’t care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. Table 7-6 shows assertion of S_PERR# that is ...
Page 60
X = don’t care 2 The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus. 3 The ...
Page 61
Master timeout on delayed transaction The device-specific P_SERR# status register reports the reason for the assertion of P_SERR#. Most of these events have additional device-specific disable bits in the P_SERR# event disable register that make it possible to mask ...
Page 62
The first locked transaction must be a memory read transaction. Subsequent locked transactions can be memory read or ...
Page 63
LOCKED TRANSACTION IN UPSTREAM DIRECTION PI7C7300A ignores upstream lock and transactions. PI7C7300A will pass these transactions as normal transactions without lock established. 8.3 ENDING EXCLUSIVE ACCESS After the lock has been acquired on both initiator and target buses, PI7C7300A ...
Page 64
PCI BUS ARBITRATION PI7C7300A must arbitrate for use of the primary bus when forwarding upstream transactions. Also, it must arbitrate for use of the secondary bus when forwarding downstream transactions. The arbiter for the primary bus resides external to ...
Page 65
The low priority group as a whole represents one entry in the high priority group; that is, if the high priority group consists of n masters, then in at least every n+1 transactions ...
Page 66
PCI clock cycle later. If the secondary PCI bus is busy, that is, either S1_FRAME# (S2_FRAME#) or S1_IRDY# (S2_IRDY#) is asserted, the arbiter can de-assert one grant and assert another grant ...
Page 67
If the internal secondary bus arbiter is enabled, the secondary bus is always parked at the last master that used the PCI bus. That is, PI7C7300A keeps the secondary bus grant asserted to a particular master until a new secondary ...
Page 68
P_CLK. The secondary clock edges are delayed from P_CLK edges by a minimum of 0ns. This is the rule for using secondary clocks: ! Each secondary clock output is limited to no more than one load. 12 ...
Page 69
S1_RESET# (S2_RESET#) assertion. All posted write and delayed transaction data buffers are reset. Therefore, any transactions residing inside the buffers at the time of secondary reset are discarded. When S1_RESET# or S2_RESET# is asserted by means of the ...
Page 70
P_CBE [3:0] # 1100 1101 1110 1111 13.2 SECONDARY INTERFACE S1_CBE [3:0] # S2_CBE [3:0] # 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 14 CONFIGURATION REGISTERS As PI7C7300A supports two secondary ...
Page 71
Secondary Bus 2 interfaces respectively. The configuration for the Primary interface is implemented through Configuration Register 1. Page 71 OF 109 PI7C7300A 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION 09/25/03 Revision 1.09 ...
Page 72
CONFIGURATION REGISTER 1 AND 2 31-24 Device ID Reserved Secondary Latency Timer Secondary Status Memory Limit Prefetchable Memory Limit I/O Limit Upper 16-bit Bridge Control Arbiter Control Upstream Memory Control Upstream ( Memory Limit Master ...
Page 73
DEVICE ID REGISTER – OFFSET 00h Configuration Register 1 Bit Function 31:16 Device ID Configuration Register 2 Bit Function 31:16 Device ID 14.1.3 COMMAND REGISTER – OFFSET 04h Bit Function 0 I/O Space Enable Memory Space 1 Enable Bus ...
Page 74
Bit Function Parity Error 6 Response Wait Cycle 7 Control 8 P_SERR# enable Fast Back-to- 9 Back Enable 15:10 Reserved 14.1.4 STATUS REGISTER – OFFSET 04h Bit Function 19:16 Reserved 20 Capabilities List 21 66MHz Capable 22 Reserved 23 Fast ...
Page 75
Bit Function 27 Signaled Target Abort 28 Received Target Abort 29 Received Master Abort 30 Signaled System Error 31 Detected Parity Error 14.1.5 REVISION ID REGISTER – OFFSET 08h Bit Function 7:0 Revision 14.1.6 CLASS CODE REGISTER – OFFEST 08h ...
Page 76
HEADER TYPE REGISTER – OFFSET 0Ch Configuration Register 1 Bit Function 23:16 Header Type Configuration Register 2 Bit Function 23:16 Header Type 14.1.10 PRIMARY BUS NUMBER REGISTER – OFFSET 18h Bit Function 7:0 Primary Bus Number 14.1.11 SECONDARY (S1 ...
Page 77
I/O BASE REGISTER – OFFSET 1Ch Bit Function 3:0 32-bit Indicator 7:4 I/O Base Address [15:12] 14.1.15 I/O LIMIT REGISTER – OFFSET 1Ch Bit Function 11:8 32-bit Indicator 15:12 I/O Base Address [15:12] 14.1.16 SECONDARY STATUS REGISTER – OFFSET ...
Page 78
Bit Function Received Target 28 Abort Received Master 29 Abort Received System 30 Error Detected Parity 31 Error 14.1.17 MEMORY BASE REGISTER – OFFSET 20h Bit Function 3:0 15:4 Memory Base Address [15:4] 14.1.18 MEMORY LIMIT REGISTER – OFFSET 20h ...
Page 79
Prefetchable Memory Base Address [31:20] 14.1.20 PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h Bit Function 19:16 64-bit addressing 31:20 Prefetchable Memory Base Address [31:20] 14.1.21 PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h Bit Function 31:0 Prefetchable ...
Page 80
I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h Bit Function 31:0 I/O Limit Address, Upper 16-bits [31:16] 14.1.25 ECP POINTER REGISTER – OFFSET 34h Bit Function 7:0 Enhanced Capabilities Port Pointer 14.1.26 BRIDGE CONTROL REGISTER – OFFSET 3Ch ...
Page 81
Bit Function 19 VGA enable 20 Reserved 21 Master Abort Mode 22 Secondary Interface Reset 23 Fast Back-to- Back Enable 24 Reserved 25 Reserved 26 Master Timeout Status 27 Discard Timer P_SERR# enable 31-28 Reserved 14.1.27 DIAGNOSTIC / CHIP CONTROL ...
Page 82
Bit Function Type Description 4 Memory Read R/W Controls whether the bridge supports memory read flow-through Flow-Through Control 0: Enable 1: Disable Reset to 0 8:5 Reserved R/O Reserved. Returns 0 when read. Reset to 0 10:9 Test Mode For ...
Page 83
ARBITER CONTROL REGISTER – OFFSET 40h Bit Function 23:16 Arbiter Control 24 Reserved 25 Priority of Secondary Interface 26 Arbiter Park Function 31:27 Reserved 14.1.29 UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h Bit Function Upstream ( ...
Page 84
Bit Function Secondary Bus Master 30:28 Preemption Control 31 Preemption 14.1.31 UPSTREAM ( MEMORY BASE REGISTER – OFFSET 50h Bit Function 3:0 64 bit addressing Upstream 15:4 Memory Base Address 14.1.32 UPSTREAM ( ...
Page 85
UPSTREAM ( MEMORY LIMIT UPPER 32 BITS REGISTER – OFFSET 58h Bit Function Upstream 31:0 Memory Limit Address 14.1.35 P_SERR# EVENT DISABLE REGISTER – OFFSET 64h Bit Function 0 Reserved Posted Write 1 Parity Error ...
Page 86
Bit Function Delayed Read – Data From Target 7 Reserved 14.1.36 SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h Configuration Register 1 Bit Function 1:0 Clock 0 disable 3:2 Clock 1 disable 5:4 Clock 2 disable 7:6 Clock 3 ...
Page 87
Bit Function Type Description Controls PI7C7300A’s detection mechanism for matching memory read retry cycles from the initiator on the primary interface 0: exact matching for non-posted memory write retry cycles from Primary MEMR initiator on the primary interface 1 Command ...
Page 88
Bit Function Enable Primary 11 To Hold Request Longer 15:12 Reserved 14.1.38 MASTER TIMEOUT COUNTER REGISTER – OFFSET 74h Bit Function 31:16 Master Timeout 14.1.39 RETRY COUNTER REGISTER – OFFSET 78h Bit Function 31:0 Retry Counter 14.1.40 SAMPLING TIMER REGISTER ...
Page 89
SECONDARY SUCCESSFUL I/O WRITE COUNTER REGISTER – OFFSET 84h Bit Function Successful I/O 31:0 Write Counts 14.1.43 SECONDARY SUCCESSFUL MEMORY READ COUNTER REGISTER – Offset 88h Bit Function Successful Memory Read 31:0 Counts on S1 ...
Page 90
PRIMARY SUCCESSFUL MEMORY READ COUNTER REGISTER – OFFSET 98h Bit Function Successful Memory Read 31:0 Counts on Primary 14.1.48 PRIMARY SUCCESSFUL MEMORY WRITE COUNTER REGISTER – OFFSET 9Ch Bit Function Successful Memory Write 31:0 Counts on Primary 14.1.49 CAPABILITY ...
Page 91
SLOT NUMBER REGISTER – OFFSET B0h Bit Function Expansion Slot 20:16 Number 21 First in Chassis 23:22 Reserved 14.1.52 CHASSIS NUMBER REGISTER – OFFSET B0h Bit Function Chassis Number 31:24 Register 14.1.53 CAPABILITY ID REGISTER – OFFSET C0h Bit ...
Page 92
Bit Function 19 LED ON/OFF 21:20 Not Available ENUM# Status – 22 Extraction ENUM# Status – 23 Insertion 31:24 Reserved 15 BRIDGE BEHAVIOR A PCI cycle is initiated by asserting the FRAME# signal bridge, there are a number ...
Page 93
TRANSACTION ORDERING To maintain data coherency and consistency, PI7C7300A complies with the ordering rules put forth in the PCI Local Bus Specification, Rev 2.2. The following table summarizes the ordering relationship of all the transactions through the bridge. PMW ...
Page 94
For reads, even parity must be generated using the initiators CBE signals combined with the read data. Again, the PAR signal corresponds to read data from the previous data phase cycle. 15.3.3 REPORTING PARITY ERRORS For all address phases, ...
Page 95
BOUNDARY SCAN ARCHITECTURE Boundary-scan test logic consists of a boundary-scan register and support logic. These are accessed through a Test Access Port (TAP). The TAP provides a simple serial interface that allows all processor signal pins to be driven ...
Page 96
TAP finite state machine outputs are decoded to select and control the test data register selected by that instruction. Upon latching, all actions caused by any previous instructions terminate. The instruction determines the test to be performed, the ...
Page 97
TAP TEST DATA REGISTERS The PI7C7300A contains two test data registers (bypass and boundary-scan). Each test data register selected by the TAP controller is connected serially between TDI and TDO. TDI is connected to the test data register’s most ...
Page 98
The bus master can be either automatic test equipment or a component (i.e., PLD) that interfaces to the TAP. The TAP controller changes state only in response to a rising edge of TCK. The value of the test mode ...
Page 99
Order Pin Names Type 46 P_AD[17] bidir 47 P_AD[17] control 48 P_AD[16] bidir 49 P_AD[16] control 50 P_CBE[2] bidir 51 P_CBE[2] control 52 P_FRAME# bidir 53 P_FRAME# control 54 P_IRDY# bidir 55 P_IRDY# control 56 P_TRDY# bidir 57 control P_DEVSEL#/P_TRDY# ...
Page 100
Order Pin Names 169 S1_AD[23] 170 S1_AD[23] 171 S1_AD[26] 172 S1_AD[26] 173 S1_AD[22] 174 S1_AD[22] 175 S1_AD[25] 176 S1_AD[25] 177 S1_AD[29] 178 S1_AD[29] 179 S1_AD[21] 180 S1_AD[21] 181 S1_AD[28] 244 S2_AD[15] 245 S2_AD[15] 246 S2_PAR 247 S2_PAR 248 S2_SERR# 249 ...
Page 101
MAXIMUM RATINGS (Above which the useful life may be impaired. For user guidelines, not tested). Storage Temperature Ambient Temperature with Power Applied Supply Voltage to Ground Potentials (Inputs and AV DC Input Voltage Note: Stresses greater than those listed ...
Page 102
AC SPECIFICATIONS Figure 17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS Symbol Parameter Tsu Input setup time to CLK – bused signals Tsu(ptp) Input setup time to CLK – point-to-point Th Input signal hold time from CLK Tval CLK to ...
Page 103
PRIMARY AND SECONDARY BUSES AT 66MHz CLOCK TIMING Symbol Parameter T SKEW among S1_CLKOUT[7:0] SKEW T SKEW among S2_CLKOUT[6:0] SKEW T DELAY between PCLK and S1_CLKOUT[7:0] DELAY T DELAY between PCLK and S2_CLKOUT[6:0] DELAY T PCLK, S1_CLKOUT[7:0] cycle time ...
Page 104
PBGA PACKAGE FIGURE Figure 18-1 272-PIN PBGA PACKAGE TOP Thermal Characteristics can be found on the web: 18.1 PART NUMBER ORDERING INFORMATION Part Number PI7C7300ANA 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION BOTTOM http://www.pericom.com/packaging/mechanicals.php Pin – Package Temperature 272 – ...
Page 105
APPENDIX A: PI7C7300A EVALUATION BOARD USER’S MANUAL GENERAL INFORMATION 1. Please make sure you have included with your PI7C7300A evaluation board, the five-page schematic and the preliminary specification for the PI7C7300A. 2. Check all jumpers for proper settings: Pin Name ...
Page 106
... Install drivers for any PCI devices you have attached to the evaluation board any of the steps are unclear or were unsuccessful, please contact your Pericom support person at 408-435-0800. 9. Thank for evaluating Pericom Semiconductor Corporation’s products. 3-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION Page 106 OF 109 PI7C7300A 09/25/03 Revision 1 ...
Page 107
FREQUENTLY ASKED QUESTIONS ! What is the function of SCAN_EN? SCAN_EN is for a full scan test or S_CLKIN select. During SCAN mode, SCAN_EN will be driven to logic “0” or “logic “1” depending on functionality. During normal mode, if ...
Page 108
What clock frequency combinations does the PI7C7300A support? Primary 66MHz 66MHz 66MHz 66MHz 33MHz 50MHz 50MHz 50MHz 50MHz 25MHz ! How are the JTAG signals being connected? The JTAG signals consist of TRST#, TCK, TMS, TDI, and TDO. All ...
Page 109
PCI-TO-PCI BRIDGE ADVANCE INFORMATION NOTES: Page 109 OF 109 PI7C7300A 09/25/03 Revision 1.09 ...