PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 48

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.3
Table 6-1 SUMMARY OF TRANSACTION ORDERING
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ORDERING RULES
Table 6-1 shows the ordering relationships of all the transactions and refers by number to
the ordering rules that follow.
Note: The superscript accompanying some of the table entries refers to any applicable
ordering rule listed in this section. Many entries are not governed by
these ordering rules; therefore, the implementation can choose whether or not the
transactions pass each other. The entries without superscripts reflect the PI7C7300A’s
implementation choices.
The following ordering rules describe the transaction relationships. Each ordering rule is
followed by an explanation, and the ordering rules are referred to by number in Table
6-1. These ordering rules apply to posted write transactions, delayed write and read
requests, and delayed write and read completion transactions crossing PI7C7300A in the
Pass
Posted Write
Delayed Read Request
Delayed Write Request
Delayed
Completion
Delayed
Completion
The ordering relationship of a transaction with respect to other transactions is
determined when the transaction completes, that is, when a transaction ends with a
termination other than target retry.
Requests terminated with target retry can be accepted and completed in any order
with respect to other transactions that have been terminated with target retry. If the
order of completion of delayed requests is important, the initiator should not start a
second delayed transaction until the first one has been completed. If more than one
delayed transaction is initiated, the initiator should repeat all delayed transaction
requests, using some fairness algorithm. Repeating a delayed transaction cannot be
contingent on completion of another delayed transaction. Otherwise, a deadlock can
occur.
Write transactions flowing in one direction have no ordering requirements with
respect to write transactions flowing in the other direction. PI7C7300A can accept
posted write transactions on both interfaces at the same time, as well as initiate
posted write transactions on both interfaces at the same time.
The acceptance of a posted memory write transaction as a target can never be
contingent on the completion of a non-locked, non-posted transaction as a master.
This is true for PI7C7300A and must also be true for other bus agents. Otherwise, a
deadlock can occur.
PI7C7300A accepts posted write transactions, regardless of the state of completion
of any delayed transactions being forwarded across PI7C7300A.
Write
Read
Posted
Write
No
No
No
No
Yes
1
2
4
3
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Delayed
Read
Request
Yes
No
No
Yes
Yes
5
Delayed
Write
Request
Yes
No
No
Yes
Yes
5
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Delayed Read
Completion
Yes
Yes
Yes
No
No
09/25/03 Revision 1.09
5
Delayed Write
Completion
Yes
Yes
Yes
No
No
PI7C7300A
5