PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 14

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Name
P_IRDY#
P_TRDY#
P_DEVSEL#
P_STOP#
P_LOCK#
P_IDSEL
P_PERR#
P_SERR#
P_REQ#
P_GNT#
P_RESET#
Pin #
V13
U13
Y14
W14
V14
Y10
Y15
W15
W6
U7
Y5
Page 14 OF 109
Type
PSTS
PSTS
PSTS
PSTS
PSTS
PI
PSTS
POD
PTS
PI
PI
Description
Primary IRDY (Active LOW). Driven by the
initiator of a transaction to indicate its ability to
complete current data phase on the primary side. Once
asserted in a data phase, it is not de-asserted until the
end of the data phase. Before tri-stated, it is driven to a
de-asserted state for one cycle.
Primary TRDY (Active LOW). Driven by the target
of a transaction to indicate its ability to complete
current data phase on the primary side. Once asserted
in a data phase, it is not de-asserted until the end of the
data phase. Before tri-stated,
it is driven to a de-asserted state for one cycle.
Primary Device Select (Active LOW). Asserted by
the target indicating that the device is accepting the
transaction. As a master, PI7C7300A waits for the
assertion of this signal within 5 cycles of P_FRAME#
assertion; otherwise, terminate with master abort.
Before tri-stated, it is driven to a
de-asserted state for one cycle.
Primary STOP (Active LOW). Asserted by the target
indicating that the target is requesting the initiator to
stop the current transaction. Before tri-stated, it is
driven to a de-asserted state for one cycle.
Primary LOCK (Active LOW). Asserted by the
master for multiple transactions to complete.
Primary ID Select. Used as a chip select line for Type
0 configuration accesses to PI7C7300A configuration
space.
Primary Parity Error (Active LOW). Asserted when
a data parity error is detected for data received on the
primary interface. Before being tri-stated, it is driven
to a de-asserted state for one cycle.
Primary System Error (Active LOW). Can be
driven LOW by any device to indicate a system error
condition. PI7C7300A drives this pin on:
!
!
!
!
!
!
!
!
!
This signal requires an external pull-up resistor for
proper operation.
Primary Request (Active LOW). This is asserted by
PI7C7300A to indicate that it wants to start a
transaction on the primary bus. PI7C7300A de-asserts
this pin for at least 2 PCI clock cycles before asserting
it again.
Primary Grant (Active LOW).
PI7C7300A can access the primary bus. During idle
and P_GNT# asserted, PI7C7300A will drive P_AD,
P_CBE, and P_PAR to valid logic levels.
Primary RESET (Active LOW).
When P_RESET# is active, all PCI signals should be
asynchronously tri-stated.
Address parity error
Posted write data parity error on target bus
Secondary S1_SERR# or S2_SERR# asserted
Master abort during posted write transaction
Target abort during posted write transaction
Posted write transaction discarded
Delayed write request discarded
Delayed read request discarded
Delayed transaction master timeout
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
When asserted,
PI7C7300A