PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 87

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Bit
1
2
3
4
8:5
9
10
Reserved
Function
Primary MEMR
Command Alias
Enable
Primary MEMW
Command Alias
Enable
Secondary
MEMR
Command Alias
Enable
Secondary
MEMW
Command Alias
Enable
Enable Long
Request
Enable
Secondary To
Hold Request
Longer
Type
R/W
R/W
R/W
R/W
R/O
R/W
R/W
Page 87 OF 109
Description
Controls PI7C7300A’s detection mechanism for matching memory
read retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from the initiator on the primary interface
Reset to 0
Controls PI7C7300A’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the primary interface
Reset to 0
Controls PI7C7300A’s detection mechanism for matching memory
read retry cycles from the initiator on S1
0: exact matching for memory read retry cycles from initiator on the
S1 or S2 interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from initiator on the S1 or S2 interface
Reset to 0
Controls PI7C7300A’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the S1 or S2 interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the S1 or S2 interface
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Controls PI7C7300A’s ability to enable long requests for lock cycles
0: normal lock operation
1: enable long request for lock cycle
Reset to 0
Control’s PI7C7300A’s ability to enable S1 or S2 to hold requests
longer.
0: internal S1 or S2 master will release REQ_L after FRAME_L
assertion
1: internal S1 or S2 master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A