PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 28

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.7.4
4.7.5
Table 4-5 READ TRANSACTION PREFETCHING
- does not matter if it is prefetchable or non-prefetchable
* don’t care
See Section 5.3 for detailed information about prefetchable and non-prefetchable address spaces.
DELAYED READ REQUESTS
PI7C7300A treats all read transactions as delayed read transactions, which means that the
read request from the initiator is posted into a delayed transaction queue. Read data from
the target is placed in the read data queue directed toward the initiator bus interface and
is transferred to the initiator when the initiator repeats the read transaction.
When PI7C7300A accepts a delayed read request, it first samples the read address, read
bus command, and address parity. When IRDY# is asserted, PI7C7300A then samples
the byte enable bits for the first data phase. This information is entered into the delayed
transaction queue. PI7C7300A terminates the transaction by signaling a target retry to the
initiator. Upon reception of the target retry, the initiator is required to continue to repeat
the same read transaction until at least one data transfer is completed, or until a target
response (target abort or master abort) other than a target retry is received.
DELAYED READ COMPLETION WITH TARGET
When delayed read request reaches the head of the delayed transaction queue,
PI7C7300A arbitrates for the target bus and initiates the read transaction only if all
previously queued posted write transactions have been delivered. PI7C7300A uses the
exact read address and read command captured from the initiator during the initial
delayed read request to initiate the read transaction. If the read transaction is a non-
prefetchable read, PI7C7300A drives the captured byte enable bits during the next cycle.
If the transaction is a prefetchable read transaction, it drives all byte enable bits to zero
for all data phases. If PI7C7300A receives a target retry in response to the read
transaction on the target bus, it continues to repeat the read transaction until at least one
data transfer is completed, or until an error condition is encountered. If the transaction is
terminated via normal master termination or target disconnect after at least one data
transfer has been completed, PI7C7300A does not initiate any further attempts to read
more data.
Memory Read
Memory Read
Memory Read Line
Memory Read Line
Memory Read Multiple
Memory Read Multiple
Type of Transaction
I/O Read
Configuration Read
Memory Read
Memory Read Line
Memory Read Multiple
Prefetchable
Prefetchable
-
-
-
-
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Read Behavior
Prefetching never allowed
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Upstream: Prefetching used or programmable
Prefetching always used
Prefetching always used
CLS = 0 or 16
CLS = 1, 2, 4, 8, 16
CLS = 0 or 16
CLS = 1, 2, 4, 8, 16
CLS = 0 or 16
CLS = 1, 2, 4, 8, 16
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
16-DWORD aligned address
boundary
Cache line address boundary
16-DWORD aligned address
boundary
Cache line boundary
32-DWORD aligned address
boundary
2X of cache line boundary
09/25/03 Revision 1.09
PI7C7300A