PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 21

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4
4.1
Table 4-1 PCI TRANSACTIONS
Types of Transactions
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PCI BUS OPERATION
This Chapter offers information about PCI transactions, transaction forwarding across
PI7C7300A, and transaction termination. The PI7C7300A has three 128-byte buffers for
buffering of upstream and downstream transactions.
commands, and byte enables and are used for both read and write transactions.
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by PI7C7300A.
Table 4-1 lists the command code and name of each PCI transaction. The Master and
Target columns indicate support for each transaction when PI7C7300A initiates
transactions as a master, on the primary (P) and secondary (S1, S2) buses, and when
PI7C7300A responds to transactions as a target, on the primary (P) and secondary (S1,
S2) buses.
As indicated in Table 4-1, the following PCI commands are not supported by
PI7C7300A:
!
!
!
Pin #
Y17
Y19
PI7C7300A never initiates a PCI transaction with a reserved command code and, as
a target, PI7C7300A ignores reserved command codes.
PI7C7300A does not generate interrupt acknowledge transactions. PI7C7300A
ignores interrupt acknowledge transactions as a target.
PI7C7300A does not respond to special cycle transactions. PI7C7300A cannot
guarantee delivery of a special cycle transaction to downstream buses because of the
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and Invalidate
Name
P_AD[11]
P_AD[5]
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Type
PB
PB
Initiates as Master
Primary
N
Y
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
Pin #
Y18
Y20
Secondary
N
Y
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
These hold addresses, data,
Name
P_AD[8]
P_AD[2]
09/25/03 Revision 1.09
Responds as Target
Primary
N
N
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
PI7C7300A
N
N
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
Type
PB
PB
Secondary