PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 49

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.4
same direction. Note that delayed completion transactions cross PI7C7300A in the
direction opposite that of the corresponding delayed requests.
1. Posted write transactions must complete on the target bus in the order in which they
2. A delayed read request traveling in the same direction as a previously queued posted
3. A delayed read completion must ‘‘pull’’ ahead of previously queued posted write
4. Delayed write requests cannot pass previously queued posted write data. For posted
5. Posted write transactions must be given opportunities to pass delayed read and write
DATA SYNCHRONIZATION
Data synchronization refers to the relationship between interrupt signaling and data
delivery. The PCI Local Bus Specification, Revision 2.2, provides the following
alternative methods for synchronizing data and interrupts:
!
!
were received on the initiator bus. The subsequent posted write transaction can be
setting a flag that covers the data in the first posted write transaction; if the second
transaction were to complete before the first transaction, a device checking the flag
could subsequently consume stale data.
write transaction must push the posted write data ahead of it. The posted write
transaction must complete on the target bus before the delayed read request can be
attempted on the target bus. The read transaction can be to the same location as the
write data, so if the read transaction were to pass the write transaction, it would
return stale data.
data traveling in the same direction. In this case, the read data is traveling in the
same direction as the write data, and the initiator of the read transaction is on the
same side of PI7C7300A as the target of the write transaction. The posted write
transaction must complete to the target before the read data is returned to the
initiator. The read transaction can be a reading to a status register of the initiator of
the posted write data and therefore should not complete until the write transaction is
complete.
memory write transactions, the delayed write transaction can set a flag that covers
the data in the posted write transaction. If the delayed write request were to complete
before the earlier posted write transaction, a device checking the flag could
subsequently consume stale data.
requests and completions. Otherwise, deadlocks may occur when some bridges
which support delayed transactions and other bridges which do not support delayed
transactions are being used in the same system. A fairness algorithm is used to
arbitrate between the posted write queue and the delayed transaction queue.
The device signaling the interrupt performs a read of the data just written (software).
The device driver performs a read operation to any register in the interrupting device
before accessing data written by the device (software).
Page 49 OF 109
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A