PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 27

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.7.2
4.7.3
Table 4-4 READ PREFETCH ADDRESS BOUNDARIES
Prefetchable behavior is used for memory read line and memory read multiple
transactions, as well as for memory read transactions that fall into prefetchable memory
space. The amount of data that is pre-fetched depends on the type of transaction. The
amount of pre-fetching may also be affected by the amount of free buffer space available
in PI7C7300A, and by any read address boundaries encountered.
Pre-fetching should not be used for those read transactions that have side effects in the
target device, that is, control and status registers, FIFOs, and so on. The target device’s
base address register or registers indicate if a memory address region is prefetchable.
NON-PREFETCHABLE READ TRANSACTIONS
A non-prefetchable read transaction is a read transaction where PI7C7300A requests one
and only one DWORD from the target and disconnects the initiator after delivery of the
first DWORD of read data. Unlike prefetchable read transactions, PI7C7300A forwards
the read byte enable information for the data phase.
Non-prefetchable behavior is used for I/O and configuration read transactions, as well as
for memory read transactions that fall into non-prefetchable memory space.
If extra read transactions could have side effects, for example, when accessing a FIFO,
use non-prefetchable read transactions to those locations. Accordingly, if it is important
to retain the value of the byte enable bits during the data phase, use non-prefetchable
read transactions. If these locations are mapped in memory space, use the memory read
command and map the target into non-prefetchable (memory-mapped I/O) memory space
to use non-prefetching behavior.
READ PREFETCH ADDRESS BOUNDARIES
PI7C7300A imposes internal read address boundaries on read pre-fetched data. When a
read transaction reaches one of these aligned address boundaries, the PI7C7300A stops
pre-fetched data, unless the target signals a target disconnect before the read pre-fetched
boundary is reached. When PI7C7300A finishes transferring this read data to the
initiator, it returns a target disconnect with the last data transfer, unless the initiator
completes the transaction before all pre-fetched read data is delivered. Any leftover pre-
fetched data is discarded.
Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB
address boundary, or until the initiator de-asserts FRAME#. Section 4.7.6 describes flow-
through mode during read operations.
Table 4-5 shows the read pre-fetch address boundaries for read transactions during non-
flow-through mode.
Type of Transaction
Configuration Read
I/O Read
Memory Read
Address Space
-
-
Non-Prefetchable
Page 27 OF 109
Cache
(CLS)
*
*
*
Line
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Size
Prefetch
Boundary
One DWORD (no prefetch)
One DWORD (no prefetch)
One DWORD (no prefetch)
09/25/03 Revision 1.09
Aligned
PI7C7300A
Address