PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 24

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.6.2
4.6.3
address out on the target bus. On the following cycle, PI7C7300A drives the first
DWORD of write data and continues to transfer write data until all write data
corresponding to that transaction is delivered, or until a target termination is received. As
long as write data exists in the queue, PI7C7300A can drive one DWORD of write data
each PCI clock cycle; that is, no master wait states are inserted. If write data is flowing
through PI7C7300A and the initiator stalls, PI7C7300A will signal the last data phase for
the current transaction at the target bus if the queue empties. PI7C7300A will restart the
follow-on transactions if the queue has new data.
PI7C7300A ends the transaction on the target bus when one of the following conditions
is met:
!
!
!
!
Section 4.9.3.2 provides detailed information about how PI7C7300A responds to target
termination during posted write transactions.
MEMORY WRITE AND INVALIDATE TRANSACTIONS
Posted write forwarding is used for Memory Write and Invalidate transactions.
The PI7C7300A disconnects Memory Write and Invalidate commands at aligned cache
line boundaries. The cache line size value in the cache line size register gives the number
of DWORD in a cache line.
If the value in the cache line size register does meet the memory write and invalidate
conditions, the PI7C7300A returns a target disconnect to the initiator either on a cache
line boundary or when the posted write buffer fills.
When the Memory Write and Invalidate transaction is disconnected before a cache line
boundary is reached, typically because the posted write buffer fills, the trans-action is
converted to Memory Write transaction.
DELAYED WRITE TRANSACTIONS
Delayed write forwarding is used for I/O write transactions and Type 1 configuration
write transactions.
A delayed write transaction guarantees that the actual target response is returned back to
the initiator without holding the initiating bus in wait states. A delayed write transaction
is limited to a single DWORD data transfer.
All posted write data has been delivered to the target.
The target returns a target disconnect or target retry (PI7C7300A starts another
transaction to deliver the rest of the write data).
The target returns a target abort (PI7C7300A discards remaining write data).
The master latency timer expires, and PI7C7300A no longer has the target bus grant
(PI7C7300A starts another transaction to deliver remaining write data).
Page 24 OF 109
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A