PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 54

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For downstream delayed write transactions, when the parity error is detected on the
initiator bus and PI7C7300A has write status to return, the following events occur:
!
!
!
Similarly, for upstream delayed write transactions, when the parity error is detected on
the initiator bus and PI7C7300A has write status to return, the following events occur:
!
!
!
For downstream transactions, where the parity error is being passed back from the target
bus and the parity error condition was not originally detected on the initiator bus, the
following events occur:
!
!
For upstream transactions, when the parity error is being passed back from the target bus
and the parity error condition was not originally detected on the initiator bus, the
following events occur:
!
!
PI7C7300A first asserts P_TRDY# and then asserts P_PERR# two cycles later, if the
primary interface parity-error-response bit is set in the command register.
PI7C7300A sets the primary interface parity-error-detected bit in the status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
PI7C7300A first asserts S1_TRDY# or S2_TRDY# and then asserts S_PERR# two
cycles later, if the secondary interface parity-error-response bit is set in the bridge
control register (offset 3Ch).
PI7C7300A sets the secondary interface parity-error-detected bit in the secondary
status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
PI7C7300A asserts P_PERR# two cycles after the data transfer, if the following are
both true:
-
-
PI7C7300A completes the transaction normally.
PI7C7300A asserts S_PERR# two cycles after the data transfer, if the following are
both true:
-
-
PI7C7300A completes the transaction normally.
The parity-error-response bit is set in the command register of the primary
interface.
The parity-error-response bit is set in the bridge control register of the
secondary interface.
The parity error response bit is set in the command register of the primary
interface.
The parity error response bit is set in the bridge control register of the secondary
interface.
Page 54 OF 109
3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A