PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 94

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.3.3
15.3.4
16
valid. For reads, even parity must be generated using the initiators CBE signals combined
with the read data. Again, the PAR signal corresponds to read data from the previous
data phase cycle.
REPORTING PARITY ERRORS
For all address phases, if a parity error is detected, the error should be reported on the
P_SERR# signal by asserting P_SERR# for one cycle and then 3-stating two cycles after
the bad address. P_SERR# can only be asserted if bit 6 and 8 in the Command Register
are both set to 1. For write data phases, a parity error should be reported by asserting the
P_PERR# signal two cycles after the data phase and should remain asserted for one cycle
when bit 6 in the Command register is set to a 1. The target reports any type of data
parity errors during write cycles, while the master reports data parity errors during read
cycles.
Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim
the bus (P_DEVSEL# remains inactive) and the cycle will then terminate with a Master
Abort. When the bridge is acting as master, a data parity error during a read cycle results
in the bridge master initiating a Master Abort.
SECONDARY IDSEL MAPPING
When PI7C7300A detects a Type 1 configuration transaction for a device connected to
the secondary, it translates the Type 1 transaction to Type 0 transaction on the
downstream interface. Type 1 configuration format uses a 5-bit field at P_AD[15:11] as a
device number. This is translated to S1_AD[31:16] or S2_AD[31:16] by PI7C7300A.
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins
are provided to support boundary scan in PI7C7300A for board-level continuity test and
diagnostics. The TAP pins assigned are TCK, TDI, TDO, TMS and TRST#. All digital
input, output, input/output pins are tested except TAP pins and clock pin.
The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and
a group of test data registers including Bypass, Device Identification and Boundary Scan
registers. The TAP controller is a synchronous 16-state machine driven by the Test Clock
(TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is
provided to ensure the machine is in TEST_LOGIC_RESET state at power-up. The
JTAG signal lines are not active when the PCI resource is operating PCI bus cycles.
PI7C7300A implements 3 basic instructions: BYPASS, SAMPLE/PRELOAD, and
EXTEST.
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3-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A