PI7C7300ANAE Pericom Semiconductor, PI7C7300ANAE Datasheet - Page 26

• Manufacturer Part Number: PI7C7300ANAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300ANAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.6.5
4.6.6
4.7
4.7.1
Table 4-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES
Note 1. Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the
configuration space.
BUFFERING MULTIPLE WRITE TRANSACTIONS
PI7C7300A continues to accept posted memory write transactions as long as space for at
least one DWORD of data in the posted write data buffer remains. If the posted write
data buffer fills before the initiator terminates the write transaction, PI7C7300A returns a
target disconnect to the initiator.
Delayed write transactions are posted as long as at least one open entry in the delayed
transaction queue exists. Therefore, several posted and delayed write transactions can
exist in data buffers at the same time. See Chapter 6 for information about how multiple
posted and delayed write transactions are ordered.
FAST BACK-TO-BACK WRITE TRANSACTIONS
PI7C7300A can recognize and post fast back-to-back write transactions. When
PI7C7300A cannot accept the second transaction because of buffer space limitations, it
returns a target retry to the initiator. The fast back-to-back enable bit must be set in the
command register for upstream write transactions, and in the bridge control register for
downstream write transactions.
READ TRANSACTIONS
Delayed read forwarding is used for all read transactions crossing PI7C7300A. Delayed
read transactions are treated as either prefetchable or non-prefetchable. Table 4-4 shows
the read behavior, prefetchable or non-prefetchable, for each type of read operation.
PREFETCHABLE READ TRANSACTIONS
A prefetchable read transaction is a read transaction where PI7C7300A performs
speculative DWORD reads, transferring data from the target before it is requested from
the initiator. This behavior allows a prefetchable read transaction to consist of multiple
data transfers. However, byte enable bits cannot be forwarded for all data phases as is
done for the single data phase of the non-prefetchable read transaction. For prefetchable
read transactions, PI7C7300A forces all byte enable bits to be turned on for all data
phases.
Type of Transaction
Delayed Write
Posted Memory Write
Posted Memory Write
Posted Memory Write and
Invalidate
Posted Memory Write and
Invalidate
bit = 0
Condition
All
Memory write disconnect control
Memory write disconnect control
bit = 1
Cache line size ≠ 1, 2, 4, 8, 16
Cache line size = 1, 2, 4, 8, 16
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3-PORT PCI-TO-PCI BRIDGE
Aligned Address Boundary
4KB aligned address boundary
Disconnects at cache line boundary
4KB aligned address boundary
Cache line boundary if posted memory
write data FIFO does not have enough
space for the cache line
Disconnects after one data transfer
ADVANCE INFORMATION
09/25/03 Revision 1.09
PI7C7300A