PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 56

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2.4
Pericom Semiconductor
Similarly, for upstream delayed write transactions, when the parity error is detected on
the initiator bus and PI7C7300D has write status to return, the following events occur:
For downstream transactions, where the parity error is being passed back from the target
bus and the parity error condition was not originally detected on the initiator bus, the
following events occur:
For upstream transactions, when the parity error is being passed back from the target bus
and the parity error condition was not originally detected on the initiator bus, the
following events occur:
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C7300D responds as a target, it
detects a data parity error on the initiator (primary) bus and the following events occur:
PI7C7300D sets the primary interface parity-error-detected bit in the status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
PI7C7300D first asserts S1_TRDY# or S2_TRDY# and then asserts S_PERR# two
cycles later, if the secondary interface parity-error-response bit is set in the bridge
control register (offset 3Ch).
PI7C7300D sets the secondary interface parity-error-detected bit in the secondary
status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
PI7C7300D asserts P_PERR# two cycles after the data transfer, if the following are
both true:
-
-
PI7C7300D completes the transaction normally.
PI7C7300D asserts S_PERR# two cycles after the data transfer, if the following are
both true:
-
-
PI7C7300D completes the transaction normally.
PI7C7300D asserts P_PERR# two cycles after the data transfer, if the parity error
response bit is set in the command register of primary interface.
PI7C7300D sets the parity error detected bit in the status register of the primary
interface.
PI7C7300D captures and forwards the bad parity condition to the secondary bus.
PI7C7300D completes the transaction normally.
The parity-error-response bit is set in the command register of the primary
interface.
The parity-error-response bit is set in the bridge control register of the
secondary interface.
The parity error response bit is set in the command register of the primary
interface.
The parity error response bit is set in the bridge control register of the secondary
interface.
Page 56 of 107
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
PI7C7300D