PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 66

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9
Pericom Semiconductor
After the lock has been acquired on both initiator and target buses, PI7C7300D must
maintain the lock on the target bus for any subsequent locked transactions until the
initiator relinquishes the lock.
The only time a target-retry causes the lock to be relinquished is on the first transaction
of a locked sequence. On subsequent transactions in the sequence, the target retry has no
effect on the status of the lock signal.
An established target lock is maintained until the initiator relinquishes the lock.
PI7C7300D does not know whether the current transaction is the last one in a sequence
of locked transactions until the initiator de-asserts the LOCK# signal at end of the
transaction.
When the last locked transaction is a delayed transaction, PI7C7300D has already
completed the transaction on the target bus. In this example, as soon as PI7C7300D
detects that the initiator has relinquished the LOCK# signal by sampling it in the de-
asserted state while FRAME# is deasserted, PI7C7300D de-asserts the LOCK# signal on
the target bus as soon as possible. Because of this behavior, LOCK# may not be de-
asserted until several cycles after the last locked transaction has been completed on the
target bus. As soon as PI7C7300D has de-asserted LOCK# to indicate the end of a
sequence of locked transactions, it resumes forwarding unlocked transactions.
When the last locked transaction is a posted write transaction, PI7C7300D de-asserts
LOCK# on the target bus at the end of the transaction because the lock was relinquished
at the end of the write transaction on the initiator bus.
When PI7C7300D receives a target abort or a master abort in response to a locked
delayed transaction, PI7C7300D returns a target abort or a master abort when the initiator
repeats the locked transaction. The initiator must then deassert LOCK# at the end of the
transaction. PI7C7300D sets the appropriate status bits, flagging the abnormal target
termination condition (see Section 4.8). Normal forwarding of unlocked posted and
delayed transactions is resumed.
When PI7C7300D receives a target abort or a master abort in response to a locked posted
write transaction, PI7C7300D cannot pass back that status to the initiator. PI7C7300D
asserts SERR# on the initiator bus when a target abort or a master abort is received
during a locked posted write transaction, if the SERR# enable bit is set in the command
register. Signal SERR# is asserted for the master abort condition if the master abort mode
bit is set in the bridge control register (see Section 7.4).
PCI BUS ARBITRATION
PI7C7300D must arbitrate for use of the primary bus when forwarding upstream
transactions. Also, it must arbitrate for use of the secondary bus when forwarding
downstream transactions. The arbiter for the primary bus resides external to PI7C7300D,
typically on the motherboard. For the secondary PCI bus, PI7C7300D implements an
internal arbiter. This arbiter can be disabled, and an external arbiter can be used instead.
This chapter describes primary and secondary bus arbitration.
Page 66 of 107
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
PI7C7300D