PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 89

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.36
14.1.37
Pericom Semiconductor
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h
Configuration Register 1
Configuration Register 2
PORT OPTION REGISTER – OFFSET 74h
Bit
6
7
Bit
1:0
3:2
5:4
7:6
9:8
11:10
13:12
15:14
Bit
1:0
3:2
5:4
7:6
9:8
11:10
13:12
15:14
Bit
0
Clock 5 disable
Clock 6 disable
Clock 7 disable
Clock 5 disable
Clock 6 disable
Clock 7 disable
Function
Delayed Read –
No Data From
Target
Reserved
Function
Clock 0 disable
Clock 1 disable
Clock 2 disable
Clock 3 disable
Clock 4 disable
Function
Clock 0 disable
Clock 1 disable
Clock 2 disable
Clock 3 disable
Clock 4 disable
Function
Reserved
Type
R/W
R/O
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
R/O
Page 89 of 107
Description
Controls PI7C7300D’s ability to assert P_SERR# when it is unable to
transfer any read data from the target after 2
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Description
If either bit is 0, then S1_CLKOUT [0] is enabled.
If both bits are 1, the S1_CLKOUT [0] is disabled.
If either bit is 0, then S1_CLKOUT [1] is enabled.
If both bits are 1, the S1_CLKOUT [1] is disabled.
If either bit is 0, then S1_CLKOUT [2] is enabled.
If both bits are 1, the S1_CLKOUT [2] is disabled.
If either bit is 0, then S1_CLKOUT [3] is enabled.
If both bits are 1, the S1_CLKOUT [3] is disabled.
If either bit is 0, then S1_CLKOUT [4] is enabled.
If both bits are 1, the S1_CLKOUT [4] is disabled.
If either bit is 0, then S1_CLKOUT [5] is enabled.
If both bits are 1, the S1_CLKOUT [5] is disabled.
If either bit is 0, then S1_CLKOUT [6] is enabled.
If both bits are 1, the S1_CLKOUT [6] is disabled.
If either bit is 0, then S1_CLKOUT [7] is enabled.
If both bits are 1, the S1_CLKOUT [7] is disabled.
Description
If either bit is 0, then S2_CLKOUT [0] is enabled.
If both bits are 1, the S2_CLKOUT [0] is disabled.
If either bit is 0, then S2_CLKOUT [1] is enabled.
If both bits are 1, the S2_CLKOUT [1] is disabled.
If either bit is 0, then S2_CLKOUT [2] is enabled.
If both bits are 1, the S2_CLKOUT [2] is disabled.
If either bit is 0, then S2_CLKOUT [3] is enabled.
If both bits are 1, the S2_CLKOUT [3] is disabled.
If either bit is 0, then S2_CLKOUT [4] is enabled.
If both bits are 1, the S2_CLKOUT [4] is disabled.
If either bit is 0, then S2_CLKOUT [5] is enabled.
If both bits are 1, the S2_CLKOUT [5] is disabled.
If either bit is 0, then S2_CLKOUT [6] is enabled.
If both bits are 1, the S2_CLKOUT [6] is disabled.
If either bit is 0, then S2_CLKOUT [7] is enabled.
If both bits are 1, the S2_CLKOUT [7] is disabled.
Description
Reserved. Returns 0 when read. Reset to 0.
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
24
attempts.
PI7C7300D