PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 85

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.1.27
Pericom Semiconductor
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h
Configuration 1
Configuration 2
Bit
0
1
3:2
4
8:5
10:9
15:11
Bit
0
1
3:2
4
8:5
10:9
15:11
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Function
Reserved
Memory Write
Disconnect
Control
Memory Read
Flow-Through
Control
Test Mode For
All Counters at P
and S1
Function
Reserved
Memory Write
Disconnect
Control at S2
Memory Read
Flow-through
Control
Test Mode For
All Counters at
S2
Type
R/O
R/W
R/O
R/W
R/O
R/O
R/O
Type
R/O
R/W
R/O
R/W
R/O
R/O
R/O
Page 85 of 107
Description
Reserved. Returns 0 when read. Reset to 0
Controls when the bridge (as a target) disconnects memory write
transactions.
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address boundary
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Controls whether the bridge supports memory read flow-through
0: Enable
1: Disable
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Controls the testability of the bridge’s internal counters.
The bits are used for chip test only.
00: all bits are exercised
01: byte 1 is exercised
10: byte 2 is exercised
11: byte 3 is exercised
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Description
Reserved. Returns 0 when read. Reset to 0
Controls when the bridge (as a target) disconnects memory write
transactions.
0: memory write disconnects at 4KB aligned address boundary
1: memory write disconnects at cache line aligned address boundary
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Controls whether the bridge supports memory read flow-through
0: Enable
1: Disable
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Controls the testability of the bridge’s internal counters.
The bits are used for chip test only.
00: all bits are exercised
01: byte 1 is exercised
10: byte 2 is exercised
11: byte 3 is exercised
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
PI7C7300D