PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 96

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.3
15.3.1
15.3.2
15.3.3
Pericom Semiconductor
In Row 1 Column 1, PMW cannot pass the previous PMW and that means they must
complete on the target bus in the order in which they were received in the initiator bus.
In Row 2 Column1,DRR cannot pass the previous PMW and that means the previous
PMW heading to the same direction must be completed before the DRR can be attempted
on the target bus.
In Row 1 Column 2, PMW can pass the previous DRR as long as the DRR reaches the
head of the delayed transaction queue.
ABNORMAL TERMINATION (INITIATED BY BRIDGE
MASTER)
MASTER ABORT
Master abort indicates that when PI7C7300D acts as a master and receives no response
(i.e., no target asserts DEVSEL# or S1_DEVSEL# or S2_DEVSEL#) from a target, the
bridge deasserts FRAME# and then deasserts IRDY#.
PARITY AND ERROR REPORTING
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR,
S1_PAR, and S2_PAR signals. Parity should be even (i. e. an even number of‘1’s) across
AD, CBE, and PAR. Parity information on PAR is valid the cycle after AD and CBE are
valid. For reads, even parity must be generated using the initiators CBE signals combined
with the read data. Again, the PAR signal corresponds to read data from the previous
data phase cycle.
REPORTING PARITY ERRORS
For all address phases, if a parity error is detected, the error should be reported on the
P_SERR# signal by asserting P_SERR# for one cycle and then 3-stating two cycles after
the bad address. P_SERR# can only be asserted if bit 6 and 8 in the Command Register
are both set to 1. For write data phases, a parity error should be reported by asserting the
P_PERR# signal two cycles after the data phase and should remain asserted for one cycle
when bit 6 in the Command register is set to a 1. The target reports any type of data
parity errors during write cycles, while the master reports data parity errors during read
cycles.
Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim
the bus (P_DEVSEL# remains inactive) and the cycle will then terminate with a Master
Abort. When the bridge is acting as master, a data parity error during a read cycle results
in the bridge master initiating a Master Abort.
DWC (Row 5)
Page 96 of 107
Yes
Yes
Yes
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
No
PI7C7300D
No