PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 9

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LIST OF TABLES
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LIST OF FIGURES
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Pericom Semiconductor
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4-1 PCI TRANSACTIONS ........................................................................................................... 21
4-2 WRITE TRANSACTION FORWARDING ........................................................................... 23
4-3 WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES ............................... 26
4-4 READ PREFETCH ADDRESS BOUNDARIES ................................................................... 29
4-5 READ TRANSACTION PREFETCHING ............................................................................. 30
4-6 DEVICE NUMBER TO IDSEL S1_AD OR S2_AD PIN MAPPING ................................... 34
4-7 DELAYED WRITE TARGET TERMINATION RESPONSE .............................................. 39
4-8 RESPONSE TO POSTED WRITE TARGET TERMINATION............................................ 39
4-9 RESPONSE TO DELAYED READ TARGET TERMINATION.......................................... 40
6-1 SUMMARY OF TRANSACTION ORDERING.................................................................... 50
7-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT ................... 58
7-2 SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT...................... 58
7-3 SETTING PRIMARY INTERFACE DATA PARITY ERROR DETECTED BIT................ 59
7-4 SETTING SECONDARY INTERFACE DATA PARITY ERROR DETECTED BIT.......... 59
7-5 ASSERTION OF P_PERR#.................................................................................................... 60
7-6 ASSERTION OF S_PERR#.................................................................................................... 62
7-7 ASSERTION OF P_SERR# FOR DATA PARITY ERRORS ............................................... 62
16-1 TAP PINS.............................................................................................................................. 99
16-2 JTAG BOUNDARY REGISTER ORDER ......................................................................... 101
9-1 SECONDARY ARBITER EXAMPLE.................................................................................. 68
16-1 TEST ACCESS PORT BLOCK DIAGRAM....................................................................... 98
17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS .............................................. 105
18-1 272-PIN PBGA PACKAGE............................................................................................... 107
Page 9 of 107
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
PI7C7300D