PI7C7300DNAE Pericom Semiconductor, PI7C7300DNAE Datasheet - Page 84

• Manufacturer Part Number: PI7C7300DNAE
• Description: IC PCI-PCI BRIDGE 3PORT 272-BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C7300DNAE

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: 272-PBGA
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 660 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pericom Semiconductor
Bit
18
19
20
21
22
23
24
25
26
27
31-28
VGA enable
Reserved
Reserved
Reserved
Reserved
Function
ISA enable
Master Abort
Mode
Secondary
Interface Reset
Fast Back-to-
Back Enable
Master Timeout
Status
Discard Timer
P_SERR# enable
Type
R/W
R/W
R/O
R/W
R/W
R/W
R/W
R/W
R/WC
R/WC
R/O
Page 84 of 107
Description
Modifies the bridge’s response to ISA I/O addresses, applying only to
those addresses falling within the I/O base and limit address registers
and within the first 64KB or PCI I/O space.
0: forward all I/O addresses in the range defined by the I/O base and
I/O limit registers
1: blocks forwarding of ISA I/O addresses in the range defined by the
I/O base and I/O limit registers that are in the first 64KB of I/O space
that address the last 768 bytes in each 1KB block. Secondary I/O
transactions are forwarded upstream if the address falls within the last
768 bytes in each 1KB block
Reset to 0
Controls the bridge’s response to VGA compatible addresses.
0: does not forward VGA compatible memory and I/O addresses from
primary to secondary
1: forward VGA compatible memory and I/O addresses from primary
to secondary regardless of other settings
Reset to 0
Reserved. Returns 0 when read. Reset to 0
Control’s bridge’s behavior responding to master aborts on secondary
interface.
0: does not report master aborts (returns FFFF_FFFFh on reads and
discards data on writes)
1: reports master aborts by signaling target abort if possible by the
assertion of P_SERR# if enabled
Reset to 0
Controls the assertion of S1_RESET# or S2_RESET# signal pin on
the secondary interface
0: does not force the assertion of S1_RESET# or S2_RESET# pin
1: forces the assertion of S1_RESET# or S2_RESET#
Reset to 0
Controls bridge’s ability to generate fast back-to-back transactions to
different devices on the secondary interface.
0: does not allow fast back-to-back transactions
1: enables fast back-to-back transactions
Reset to 0
Reserved. Reset to 0
Reserved. Reset to 0
This bit is set to 1 when either the primary master timeout counter or
secondary master timeout counter expires.
Reset to 0
This bit Is set to 1 and P_SERR# is asserted when either the primary
discard timer or the secondary S1 or S2 discard timer expire.
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
3-PORT PCI-TO-PCI BRIDGE
November 2005 - Revision 1.01
PI7C7300D