MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 114

MC68HC705X32CFU

Manufacturer Part Number
MC68HC705X32CFU
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC705X32CFU

Cpu Family
HC05
Device Core Size
8b
Frequency (max)
4MHz
Interface Type
SCI
Program Memory Type
EPROM
Program Memory Size
32KB
Total Internal Ram Size
528Byte
# I/os (max)
32
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
PQFP
Lead Free Status / Rohs Status
Supplier Unconfirmed

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC705X32CFU4
Manufacturer:
FREESCALE
Quantity:
20 000
7
CPOL – Clock polarity
This bit allows the user to select the polarity of the clocks to be sent to the SCLK pin. It works in
conjunction with the CPHA bit to produce the desired clock-data relation (see
Figure
This bit should not be manipulated while the transmitter is enabled.
CPHA – Clock phase
This bit allows the user to select the phase of the clocks to be sent to the SCLK pin. This bit works
in conjunction with the CPOL bit to produce the desired clock-data relation (see
Figure
This bit should not be manipulated while the transmitter is enabled.
(CPOL = 1, CPHA = 1)
(CPOL = 0, CPHA = 0)
(CPOL = 0, CPHA = 1)
(CPOL = 1, CPHA = 0)
7-10).
7-10).
1 (set)
0 (clear) –
1 (set)
0 (clear) –
clock
clock
clock
clock
data
Idle or preceding
transmission
Freescale Semiconductor, Inc.
Steady high value at SCLK pin outside transmission window.
Steady low value at SCLK pin outside transmission window.
SCLK clock line activated at beginning of data bit.
SCLK clock line activated in middle of data bit.
Figure 7-9 SCI data clock timing diagram (M=0)
For More Information On This Product,
Start
Start
SERIAL COMMUNICATIONS INTERFACE
LSB
0
Go to: www.freescale.com
1
2
M = 0 (8 data bits)
3
*
LBCL bit controls last data clock
4
5
6
MSB
*
*
7
*
*
Stop
Stop
MC68HC05X16
Figure 7-9
Figure 7-9
Idle or next
transmission
Rev. 1
and
and

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