MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 57

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

A mask option is provided to enable resistive pull downs on all port B pins that are programmed
as inputs.
4.3
In addition to the standard port functions described for ports A and B, port C pin 2 can be
configured, using the ECLK bit of the EEPROM/ECLK control register, to output the CPU clock. If
this is selected the corresponding DDR bit is automatically set and bit 2 of port C will always read
the output data latch. The other port C pins are not affected by this feature.
A mask option is provided to enable resistive pull downs on all port C pins that are programmed
as inputs.
ECLK — External clock option bit
The ECLK bit is cleared by power-on or external reset. It is not affected by the execution of a STOP
or WAIT instruction.
The timing diagram of the clock output is shown in
MC68HC05X16
EEPROM/ECLK control
1 (set)
0 (clear) –
Internal clock (PHI2)
External clock (ECLK/PC2)
Output port (if write to output port)
Port C
Freescale Semiconductor, Inc.
–
For More Information On This Product,
ECLK CPU clock is output on PC2.
ECLK CPU clock is not output on PC2; port C acts as a normal I/O port.
Address
Go to: www.freescale.com
$0007
Figure 4-2 ECLK timing diagram
INPUT/OUTPUT PORTS
bit 7
0
bit 6
0
bit 5
Figure
0
bit 4
4-2.
0
ECLK E1ERA E1LAT E1PGM 0000 0000
bit 3
bit 2
bit 1
bit 0
on reset
State
4-3
4