MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 78

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

5
5.3.8
This register can only be accessed when the reset request bit in the CCNTRL register is set.
SAMP — Sampling
This bit determines the number of samples of the serial bus to be taken per bit time. When set three
samples per bit are taken. This sample rate gives better rejection of noise on the bus, but
introduces a one bit delay to the bus sampling. For higher bit rates SAMP should be cleared, which
means that only one sample will be taken per bit.
TSEG22 – TSEG10 — Time segment bits
Time segments within the bit time fix the number of clock cycles per bit time, and the location of
the sample point.
SYNC_SEG
Transmit point
Sample point
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of
bus clock cycles (
Transmit point
MCAN bus timing 1 (CBT1)
SYNC_SEG
1 (set)
0 (clear) –
MCAN bus timing register 1 (CBT1)
–
t
System expects transitions to occur on the bus during this period.
A node in transmit mode will transfer a new value to the MCAN bus at this point.
A node in receive mode will sample the bus at this point. If the three samples per
bit option is selected then this point marks the position of the third sample.
SCL
Freescale Semiconductor, Inc.
) per bit (as shown above).
Three samples per bit.
One sample per bit.
For More Information On This Product,
Figure 5-5 Segments within the bit time
1 clock cycle
Address
MOTOROLA CAN MODULE (MCAN)
$0027
t
SCL
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TSEG 1
SAMP TSEG22TSEG21TSEG20TSEG13TSEG12TSEG11TSEG10 Undefined
bit 7
BIT_TIME
bit 6
bit 5
Sample point
bit 4
bit 3
TSEG 2
bit 2
Transmit point
bit 1
MC68HC05X16
SYNC_SEG
bit 0
Table
on reset
State
Rev. 1
5-3.