MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 196

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

15
(1) This register is implemented in EPROM; therefore reset has no effect on the individual bits. However, please read the important note on page B-1.
B.7
WOI — Wired-OR interrupt enable
The WOI bit can be used to enable the wired-OR interrupt (WOI) on all port B pins that have been
programmed as inputs. WOI is activated if the WOI bit is set and if the WOIE bit in the OPTR
register is also set.
DIV2, DIV8 — Clock divide ratio selection
The DIV2 and DIV8 bits are used to select the CPU clock divide ratio (see
divide-by-two clock ratio is forced in bootstrap mode, regardless of the DIV2 and DIV8 values.
RTIM — Reset time
This bit can modify the time t
RWAT — Watchdog after reset
This bit can modify the status of the watchdog counter after reset.
Mask option register (MOR)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Mask option register (MOR)
–
–
–
Freescale Semiconductor, Inc.
EPROM/EEPROM/ECLK control register is set.
EPROM/EEPROM/ECLK control register.
external reset (except in bootstrap mode).
Wired-OR interrupts are enabled, provided the WOIE bit in the
Wired-OR interrupts are disabled, irrespective of the WOIE bit in the
t
t
The watchdog will be active immediately following power-on or
The watchdog system will be disabled after power-on or external reset.
PORL
PORL
(1)
For More Information On This Product,
= 16 cycles.
= 4064 cycles.
PORL
Table B-4 Clock divide ratio selection
Address
$7FDE
DIV2
, where the RESET pin is kept low after a power-on reset.
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1
1
0
0
bit 7
WOI
MC68HC705X32
DIV8
DIV2
bit 6
1
0
1
0
DIV8
bit 5
Clock divide ratio
RTIM
10
bit 4
2
4
8
RWAT WWAT PBPD PCPD Not affected
bit 3
bit 2
Table
bit 1
B-4). Note that a
MC68HC05X16
bit 0
on reset
State
Rev. 1