C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 133

• Manufacturer Part Number: C8051F502-IMR
• Description: MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F502-IMR

• Package: 32QFN EP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/UART
• On-chip Adc: 32-chx12-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 4

15.4. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of V
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
The following guidelines are recommended for any system which contains routines which write or erase
Flash from code.
15.4.1. V
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient protection
2. The on-chip V
3. As an added precaution, explicitly enable the V
4. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment operators
5. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a 1. Areas to check
15.4.2. PSWE Maintenance
1. Reduce the number of places in code where the PSWE bit (b0 in PSCTL) is set to a 1. There should be
2. Minimize the number of variable accesses while PSWE is set to a 1. Handle pointer address updates
3. Disable interrupts prior to setting PSWE to a 1 and leave them disabled until after PSWE has been
4. Make certain that the Flash write and erase pointer variables are not located in XRAM. See your
5. Add address bounds checking to the routines that write or erase Flash memory to ensure that a routine
devices to the power supply to ensure that the supply voltages listed in the Absolute Maximum Ratings
table are not exceeded.
disabled by the firmware, use the following recommendations when re-enabling the V
on the V
set of instructions executed after the Reset Vector. For C-based systems, this will involve modifying the
startup code added by the C compiler. See your compiler documentation for more details. Make certain
that there are no delays in software between enabling the V
a reset source. Code examples showing this can be found in “AN201: Writing to Flash from Firmware",
available from the Silicon Laboratories web site.
source inside the functions that write and erase Flash memory. The V
should be placed just after the instruction to set PSWE to a 1, but before the Flash write or erase
operation instruction.
and explicitly DO NOT use the bit-wise operators (such as AND or OR). For example, "RSTSRC =
0x02" is correct. "RSTSRC |= 0x02" is incorrect.
are initialization code which enables other reset sources, such as the Missing Clock Detector or
Comparator, for example, and instructions which force a Software Reset. A global search on "RSTSRC"
can quickly verify this.
exactly one routine in code that sets PSWE to a 1 to write Flash bytes and one routine in code that sets
PSWE and PSEE both to a 1 to erase Flash pages.
and loop variable maintenance outside the "PSWE = 1;... PSWE = 0;" area. Code examples showing
this can be found in ”AN201: Writing to Flash from Firmware" available from the Silicon Laboratories
web site.
reset to '0'. Any interrupts posted during the Flash write or erase operation will be serviced in priority
order after the Flash operation has been completed and interrupts have been re-enabled by software.
compiler documentation for instructions regarding how to explicitly locate variables in different memory
areas.
called with an illegal address does not result in modification of the Flash.
DD
DD
Maintenance and the V
monitor and enable it as a reset source as early in code as possible. This should be the first
DD
monitor is turned on and enabled as a reset source by default by the hardware. If it is
DD
, system clock frequency, or temperature. This accidental execution of Flash modi-
DD
monitor
Rev. 1.2
DD
monitor and enable the V
DD
monitor and enabling the V
C8051F50x/F51x
DD
monitor enable instructions
DD
monitor as a reset
DD
monitor. Turn
DD
monitor as
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