C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 8

• Manufacturer Part Number: C8051F502-IMR
• Description: MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F502-IMR

• Package: 32QFN EP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/UART
• On-chip Adc: 32-chx12-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 4

C8051F50x/F51x
List of Figures
8
Figure 1.1. C8051F500/1/4/5 Block Diagram .......................................................... 17
Figure 1.2. C8051F508/9-F510/1 Block Diagram .................................................... 18
Figure 1.3. C8051F502/3/6/7 Block Diagram .......................................................... 19
Figure 3.1. QFP-48 Pinout Diagram (Top View) ...................................................... 25
Figure 3.2. QFN-48 Pinout Diagram (Top View) ..................................................... 26
Figure 3.3. QFN-40 Pinout Diagram (Top View) ..................................................... 27
Figure 3.4. QFP-32 Pinout Diagram (Top View) ...................................................... 28
Figure 3.5. QFN-32 Pinout Diagram (Top View) ..................................................... 29
Figure 4.1. QFP-48 Package Drawing ..................................................................... 30
Figure 4.2. QFP-48 Landing Diagram ..................................................................... 31
Figure 4.3. QFN-48 Package Drawing .................................................................... 32
Figure 4.4. QFN-48 Landing Diagram ..................................................................... 33
Figure 4.5. Typical QFN-40 Package Drawing ........................................................ 34
Figure 4.6. QFN-40 Landing Diagram ..................................................................... 35
Figure 4.7. QFP-32 Package Drawing ..................................................................... 36
Figure 4.8. QFP-32 Package Drawing ..................................................................... 37
Figure 4.9. QFN-32 Package Drawing .................................................................... 38
Figure 4.10. QFN-32 Package Drawing .................................................................. 39
Figure 5.1. Minimum VDD Monitor Threshold vs. System Clock Frequency ........... 44
Figure 6.1. ADC0 Functional Block Diagram ........................................................... 52
Figure 6.2. ADC0 Tracking Modes .......................................................................... 54
Figure 6.3. 12-Bit ADC Tracking Mode Example ..................................................... 55
Figure 6.4. 12-Bit ADC Burst Mode Example With Repeat Count Set to 4 ............. 56
Figure 6.5. ADC0 Equivalent Input Circuit ............................................................... 58
Figure 6.6. ADC Window Compare Example: Right-Justified Data ......................... 69
Figure 6.7. ADC Window Compare Example: Left-Justified Data ........................... 69
Figure 6.8. ADC0 Multiplexer Block Diagram .......................................................... 70
Figure 7.1. Temperature Sensor Transfer Function ................................................ 72
Figure 8.1. Voltage Reference Functional Block Diagram ....................................... 73
Figure 9.1. Comparator Functional Block Diagram ................................................. 75
Figure 9.2. Comparator Hysteresis Plot .................................................................. 76
Figure 9.3. Comparator Input Multiplexer Block Diagram ........................................ 81
Figure 10.1. External Capacitors for Voltage Regulator Input/Output—
Figure 10.2. External Capacitors for Voltage Regulator Input/Output—
Figure 11.1. CIP-51 Block Diagram ......................................................................... 87
Figure 12.1. C8051F50x-F51x Memory Map ........................................................... 97
Figure 12.2. Flash Program Memory Map ............................................................... 98
Figure 13.1. SFR Page Stack ................................................................................ 101
Figure 13.2. SFR Page Stack While Using SFR Page 0x0 To Access SPI0DAT . 102
Figure 13.3. SFR Page Stack After CAN0 Interrupt Occurs .................................. 103
Figure 13.4. SFR Page Stack Upon PCA Interrupt Occurring During a CAN0 ISR 104
Regulator Enabled .............................................................................. 84
Regulator Disabled ............................................................................. 85
Rev. 1.2