C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 5
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C8051F502-IMR
Manufacturer Part Number
C8051F502-IMR
Description
MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F502-IM.pdf
(312 pages)
Specifications of C8051F502-IMR
Package
32QFN EP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Ram Size
4.25 KB
Program Memory Size
64 KB
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
25
Interface Type
I2C/SPI/UART
On-chip Adc
32-chx12-bit
Operating Temperature
-40 to 125 °C
Number Of Timers
4
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19. Oscillators and Clock Selection ......................................................................... 165
20. Port Input/Output ................................................................................................. 177
21. Local Interconnect Network (LIN)....................................................................... 201
18.5. Memory Mode Selection................................................................................ 155
18.6. Timing .......................................................................................................... 156
19.1. System Clock Selection................................................................................. 165
19.2. Programmable Internal Oscillator .................................................................. 167
19.3. Clock Multiplier .............................................................................................. 170
19.4. External Oscillator Drive Circuit..................................................................... 172
20.1. Port I/O Modes of Operation.......................................................................... 178
20.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 179
20.3. Priority Crossbar Decoder ............................................................................. 180
20.4. Port I/O Initialization ...................................................................................... 182
20.5. Port Match ..................................................................................................... 187
20.6. Special Function Registers for Accessing and Configuring Port I/O ............. 191
21.1. Software Interface with the LIN Controller..................................................... 202
21.2. LIN Interface Setup and Operation................................................................ 202
21.3. LIN Master Mode Operation .......................................................................... 205
21.4. LIN Slave Mode Operation ............................................................................ 206
18.5.1. Internal XRAM Only .............................................................................. 155
18.5.2. Split Mode without Bank Select............................................................. 155
18.5.3. Split Mode with Bank Select.................................................................. 156
18.5.4. External Only......................................................................................... 156
18.6.1. Non-Multiplexed Mode .......................................................................... 158
18.6.2. Multiplexed Mode .................................................................................. 161
19.2.1. Internal Oscillator Suspend Mode ......................................................... 167
19.4.1. External Crystal Example...................................................................... 174
19.4.2. External RC Example............................................................................ 175
19.4.3. External Capacitor Example.................................................................. 175
20.1.1. Port Pins Configured for Analog I/O...................................................... 178
20.1.2. Port Pins Configured For Digital I/O...................................................... 178
20.1.3. Interfacing Port I/O in a Multi-Voltage System ...................................... 179
20.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 179
20.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 179
20.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 180
21.2.1. Mode Definition ..................................................................................... 202
21.2.2. Baud Rate Options: Manual or Autobaud ............................................. 202
21.2.3. Baud Rate Calculations: Manual Mode................................................. 202
21.2.4. Baud Rate Calculations—Automatic Mode ........................................... 204
18.6.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111............................. 158
18.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111 ....... 159
18.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110 ....................... 160
18.6.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011............................. 161
18.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011 ....... 162
18.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010 ....................... 163
Rev. 1.2
C8051F50x/F51x
5
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