C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 195
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C8051F502-IMR
Manufacturer Part Number
C8051F502-IMR
Description
MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F502-IM.pdf
(312 pages)
Specifications of C8051F502-IMR
Package
32QFN EP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Ram Size
4.25 KB
Program Memory Size
64 KB
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
25
Interface Type
I2C/SPI/UART
On-chip Adc
32-chx12-bit
Operating Temperature
-40 to 125 °C
Number Of Timers
4
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SFR Definition 20.19. P1SKIP: Port 1 Skip
SFR Address = 0xD5; SFR Page = 0x0F
SFR Definition 20.20. P2: Port 2
SFR Address = 0xA0; SFR Page = All Pages; Bit-Addressable
Reset
Reset
Name
Name
Bit
7:0
Bit
7:0
Type
Type
Bit
Bit
P1SKIP[7:0]
P2[7:0]
Name
Name
7
0
7
1
Port 2Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Port 1 Crossbar Skip Enable Bits.
These bits select Port 1 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P1.n pin is not skipped by the Crossbar.
1: Corresponding P1.n pin is skipped by the Crossbar.
0
1
6
6
Description
5
0
5
1
Rev. 1.2
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
4
0
4
1
P1SKIP[7:0]
P2[7:0]
R/W
R/W
Function
Write
3
0
3
1
C8051F50x/F51x
2
0
2
1
0: P2.n Port pin is logic
LOW.
1: P2.n Port pin is logic
HIGH.
1
0
1
1
Read
0
0
0
1
195
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