C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 261
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C8051F502-IMR
Manufacturer Part Number
C8051F502-IMR
Description
MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F502-IM.pdf
(312 pages)
Specifications of C8051F502-IMR
Package
32QFN EP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Ram Size
4.25 KB
Program Memory Size
64 KB
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
25
Interface Type
I2C/SPI/UART
On-chip Adc
32-chx12-bit
Operating Temperature
-40 to 125 °C
Number Of Timers
4
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SFR Definition 25.3. SPI0CKR: SPI0 Clock Rate
SFR Address = 0xA2; SFR Page = 0x00
SFR Definition 25.4. SPI0DAT: SPI0 Data
SFR Address = 0xA3; SFR Page = 0x00
Name
Reset
Name
Reset
Bit
7:0
Bit
7:0
Type
Type
Bit
Bit
SPI0DAT[7:0] SPI0 Transmit and Receive Data.
SCR[7:0]
Name
Name
7
0
7
0
SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided ver-
sion of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
f SCK
f SCK
6
0
6
0
=
=
----------------------------- -
2
--------------------------------------------------------------- -
2
2000000
x
x
5
0
5
0
4
SPI0CKR[7:0]
+
SYSCLK
1
Rev. 1.2
SPI0DAT[7:0]
4
0
4
0
SCR[7:0]
f SCK
+
R/W
R/W
1
Function
Function
=
3
0
3
0
200 kHz
C8051F50x/F51x
2
0
2
0
1
0
1
0
0
0
0
0
261
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