C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 265

• Manufacturer Part Number: C8051F502-IMR
• Description: MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F502-IMR

• Package: 32QFN EP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/UART
• On-chip Adc: 32-chx12-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 4

26. Timers
Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the
standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose
use. These timers can be used to measure time intervals, count external events and generate periodic
interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary modes of operation.
Timer 2 and Timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload.
Timers 0 and 1 may be clocked by one of five sources, determined by the Timer Mode Select bits (T1M –
T0M) and the Clock Scale bits (SCA1 – SCA0). The Clock Scale bits define a pre-scaled clock from which
Timer 0 and/or Timer 1 may be clocked (See SFR Definition 26.1 for pre-scaled clock selection).Timer 0/1
may then be configured to use this pre-scaled clock signal or the system clock.
Timer 2 and Timer 3 may be clocked by the system clock, the system clock divided by 12, or the external
oscillator clock source divided by 8.
Timer 0 and Timer 1 may also be operated as counters. When functioning as a counter, a counter/timer
register is incremented on each high-to-low transition at the selected input pin (T0 or T1). Events with a fre-
quency of up to one-fourth the system clock frequency can be counted. The input signal need not be peri-
odic, but it should be held at a given level for at least two full system clock cycles to ensure the level is
properly sampled.
13-bit counter/timer
16-bit counter/timer
8-bit counter/timer with 
auto-reload
Two 8-bit counter/timers (Timer 0
only)
Timer 0 and Timer 1 Modes
16-bit timer with auto-reload
Two 8-bit timers with auto-reload
Timer 2 Modes
Rev. 1.2
C8051F50x/F51x
16-bit timer with auto-reload
Two 8-bit timers with auto-reload
Timer 3 Modes
265