C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 208

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C8051F502-IMR

Manufacturer Part Number
C8051F502-IMR
Description
MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051F502-IMR

Package
32QFN EP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Ram Size
4.25 KB
Program Memory Size
64 KB
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
25
Interface Type
I2C/SPI/UART
On-chip Adc
32-chx12-bit
Operating Temperature
-40 to 125 °C
Number Of Timers
4

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21.7. LIN Registers
The following Special Function Registers (SFRs) and indirect registers are available for the LIN controller.
21.7.1. LIN Direct Access SFR Registers Definitions
SFR Definition 21.1. LIN0ADR: LIN0 Indirect Address Register
SFR Address = 0xD3; SFR Page = 0x00
SFR Definition 21.2. LIN0DAT: LIN0 Indirect Data Register
SFR Address = 0xD2; SFR Page = 0x00
208
Name
Reset
Name
Reset
7:0 LIN0ADR[7:0] LIN Indirect Address Register Bits.
7:0 LIN0DAT[7:0] LIN Indirect Data Register Bits.
Bit
Bit
Type
Type
Bit
Bit
Name
Name
7
0
7
0
This register hold an 8-bit address used to indirectly access the LIN0 core registers.
Table 21.4 lists the LIN0 core registers and their indirect addresses. Reads and
writes to LIN0DAT will target the register indicated by the LIN0ADR bits.
When this register is read, it will read the contents of the LIN0 core register pointed
to by LIN0ADR.
When this register is written, it will write the value to the LIN0 core register pointed
to by LIN0ADR.
6
0
6
0
5
0
5
0
Rev. 1.2
LIN0ADR[7:0]
4
0
4
LIN0DAT[7:0]
0
R/W
R/W
Function
Function
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0

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