C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 209

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C8051F502-IMR

Manufacturer Part Number
C8051F502-IMR
Description
MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051F502-IMR

Package
32QFN EP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Ram Size
4.25 KB
Program Memory Size
64 KB
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
25
Interface Type
I2C/SPI/UART
On-chip Adc
32-chx12-bit
Operating Temperature
-40 to 125 °C
Number Of Timers
4

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0
SFR Definition 21.3. LIN0CF: LIN0 Control Mode Register
SFR Address = 0xC9; SFR Page = 0x0F
Name
Reset
Bit
4:0
Type
7
6
5
Bit
ABAUD
Unused
LINEN
MODE
LINEN
Name
R/W
7
0
MODE
LIN Interface Enable Bit.
0: LIN0 is disabled.
1: LIN0 is enabled.
LIN Mode Selection Bit.
0: LIN0 operates in slave mode.
1: LIN0 operates in master mode.
LIN Mode Automatic Baud Rate Selection.
This bit only has an effect when the MODE bit is configured for slave mode.
0: Manual baud rate selection is enabled.
1: Automatic baud rate selection is enabled.
Read = 00000b; Write = Don’t Care
R/W
6
1
ABAUD
R/W
5
1
R
4
0
Rev. 1.2
Function
R
3
0
C8051F50x/F51x
R
2
0
R
1
0
R
0
0
209

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