C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 63

• Manufacturer Part Number: C8051F502-IMR
• Description: MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F502-IMR

• Package: 32QFN EP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/UART
• On-chip Adc: 32-chx12-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 4

SFR Definition 6.4. ADC0CF: ADC0 Configuration
SFR Address = 0xBC; SFR Page = 0x00
Reset
Name
Bit
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Period Bits.
2:1
Type
0
Bit
A0RPT[1:0] ADC0 Repeat Count
GAINEN
Name
7
1
SAR Conversion clock is derived from system clock by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC4 – 0. SAR Conversion clock
requirements are given in the ADC specification table
BURSTEN = 0: FCLK is the current system clock
BURSTEN = 1: FLCLK is a maximum of 30 Mhz, independent of the current system
clock..
Note: Round up the result of the calculation for AD0SC
Controls the number of conversions taken and accumulated between ADC0 End of
Conversion (ADCINT) and ADC0 Window Comparator (ADCWINT) interrupts. A con-
vert start is required for each conversion unless Burst Mode is enabled. In Burst
Mode, a single convert start can initiate multiple self-timed conversions. Results in
both modes are accumulated in the ADC0H:ADC0L register. When AD0RPT1–0 are
set to a value other than '00', the AD0LJST bit in the ADC0CN register must be
set to '0' (right justified).
00: 1 conversion is performed.
01: 4 conversions are performed and accumulated.
10: 8 conversions are performed and accumulated.
11: 16 conversions are performed and accumulated.
Gain Enable Bit.
Controls the gain programming. Refer to Section “6.3. Selectable Gain” on page 58
for information about using this bit.
AD0SC
1
6
=
AD0SC[4:0]
-------------------- 1
CLK
R/W
FCLK
5
1
SAR
–
Rev. 1.2
4
1
Function
3
1
C8051F50x/F51x
R/W
2
AD0RPT[1:0]
0
R/W
1
0
GAINEN
R/W
0
0
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