C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 137

• Manufacturer Part Number: C8051F502-IMR
• Description: MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F502-IMR

• Package: 32QFN EP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/UART
• On-chip Adc: 32-chx12-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 4

SFR Definition 15.4. CCH0CN: Cache Control
SFR Address = 0xE3; SFR Page = 0x0F
SFR Definition 15.5. ONESHOT: Flash Oneshot Period
SFR Address = 0xBE; SFR Page = 0x0F
Reset
Reset
Name Reserved
Name
Bit
7:6
4:1
Bit
7:4
3:0
Type
Type
5
0
Bit
Bit
PERIOD[3:0] Oneshot Period Control Bits.
Reserved
Reserved
CHBLKW
CHPFEN
Name
Unused
Name
R/W
R
7
0
7
0
Must Write 00b
Cache Prefect Enable Bit.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
Must Write 0000b.
Block Write Enable Bit.
This bit allows block writes to Flash memory from firmware.
0: Each byte of a software Flash write is written individually.
1: Flash bytes are written in groups of two.
Reserved
Read = 0000b. Write = don’t care.
These bits limit the internal Flash read strobe width as follows. When the Flash read
strobe is de-asserted, the Flash memory enters a low-power state for the remainder
of the system clock cycle. These bits have no effect when the system clocks is
greater than 12.5 MHz and FLRT = 0.
R/W
R
0
0
6
6
CHPFEN
R/W
R
5
1
5
0
FLASH
Reserved
R/W
Rev. 1.2
R
4
0
4
0
RDMAX
Function
Reserved
Function
=
R/W
R/W
5ns
3
0
3
1
+

PERIOD 5ns
Reserved
C8051F50x/F51x
R/W
R/W
2
0
2
1
PERIOD[3:0]


Reserved
R/W
R/W
1
0
1
1
CHBLKW
R/W
R/W
0
0
0
1
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