AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 183

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.6.4.1
32072G–11/2011
Read waveforms
•NRD waveform
•NCS waveform
access type. NWR0 to NWR1 have the same timings and protocol as NWE. In the same way,
NCS represents one of the NCS[0..5] chip select lines.
The read cycle is shown on
The read cycle starts with the address setting on the memory address bus, i.e.:
Figure 15-7. Standard Read Cycle
The NRD signal is characterized by a setup timing, a pulse width, and a hold timing.
Similarly, the NCS signal can be divided into a setup time, pulse length and hold time.
NBS0, NBS1,
1. NRDSETUP: the NRD setup time is defined as the setup of address before the NRD
2. NRDPULSE: the NRD pulse length is the time between NRD falling edge and NRD ris-
3. NRDHOLD: the NRD hold time is defined as the hold time of address after the NRD ris-
A[AD_MSB:2]
A0, A1
falling edge.
ing edge.
ing edge.
{A[23:2], A1, A0} for 8-bit devices
{A[23:2], A1} for 16-bit devices
D[15:0]
CLK_SMC
NRD
NCS
NCSRDSETUP
NRDSETUP
Figure 15-7 on page
NCSRDPULSE
NRDPULSE
NRDCYCLE
183.
NRDHOLD
NCSRDHOLD
183