AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 373

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.12.20 Last Source Transaction Request Register
Name:
Access Type:
Offset:
Reset Value:
A bit is assigned for each channel in this register. LstSrcReg[n] is ignored when software handshaking is not enabled for
the source of channel n.
A channel LSTSRC bit is written only if the corresponding channel write enable bit in the LSTSRC_WE field is asserted on
the same System Bus write transfer.
• LSTSRC_WE[11:8]: Source Last Transaction request write enable
• LSTSRC[3:0]: Source Last Transaction request
32072G–11/2011
31
23
15
7
-
-
-
-
0 = Write disabled
1 = Write enabled
30
22
14
6
-
-
-
-
LstSrcReg
Read/write
0x388
0x0000000
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
LSTSRC_W
LSTSRC3
E3
27
19
11
3
-
-
LSTSRC_W
LSTSRC2
E2
26
18
10
2
-
-
LSTSRC_W
LSTSRC1
E1
25
17
9
1
-
-
LSTSRC_W
LSTSRC0
E0
24
16
8
0
-
-
373