AT32UC3A4128S Atmel Corporation, AT32UC3A4128S Datasheet - Page 357

• Manufacturer Part Number: AT32UC3A4128S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A4128S

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.12.6
Name:
Access Type:
Offset:
• Reset Value: 0x00000C00 + [x * 0x20]
•
The DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A
new block transfer is then initiated.
• RELOAD_SRC: Automatic Source Reload
The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A
new block transfer is then initiated.
• SRC_HS_POL: Source Handshaking Interface Polarity
• DST_HS_POL: Destination Handshaking Interface Polarity
• HS_SEL_SRC: Source Software or Hardware Handshaking Select
This register selects which of the handshaking interfaces, hardware or software, is active for source requests on this
channel.
If the source peripheral is memory, then this bit is ignored.
• HS_SEL_DST: Destination Software or Hardware Handshaking Select
This register selects which of the handshaking interfaces, hardware or software, is active for destination requests on this
channel.
32072G–11/2011
RELOAD_D
RELOAD_DST: Automatic Destination Reload
ST
31
23
15
7
-
0 = Active high
1 = Active low
0 = Active high
1 = Active low
0 = Hardware handshaking interface. Software-initiated transaction requests are ignored.
1 = Software handshaking interface. Hardware-initiated transaction requests are ignored.
Configuration Register for Channel x Low
-
RELOAD_S
CH_PRIOR
RC
30
22
14
6
-
CFGxL
Read/Write
0x040 + [x * 0x58]
29
21
13
5
-
-
-
28
20
12
4
-
-
-
HS_SEL_SR
SRC_HS_P
OL
27
19
11
C
3
-
-
DST_HS_PO
HS_SEL_DS
26
18
10
L
T
2
-
-
FIFO_EMPT
25
17
Y
9
1
-
-
-
CH_SUSP
24
16
8
0
-
-
-
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